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The 18th Asia and South Pacific Design Automation Conference

Session 4B  Memory Hierarchy Optimization
Time: 10:20 - 12:20 Thursday, January 24, 2013
Chair: Jason Xue (City Univ. of Hong Kong, Hong Kong)

4B-1 (Time: 10:20 - 10:50)
TitleTRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs
Author*Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo (National Univ. of Singapore, Singapore)
Pagepp. 320 - 325
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4B-2 (Time: 10:50 - 11:20)
TitleOptimizing Translation Information Management in NAND Flash Memory Storage Systems
Author*Qi Zhang, Xuandong Li, Linzhang Wang, Tian Zhang (Nanjing Univ., China), Yi Wang, Zili Shao (Hong Kong Polytechnic Univ., Hong Kong)
Pagepp. 326 - 331
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4B-3 (Time: 11:20 - 11:50)
TitleAn Adaptive Filtering Mechanism for Energy Efficient Data Prefetching
Author*Xianglei Dang, Xiaoyin Wang, Dong Tong, Zichao Xie, Lingda Li, Keyi Wang (Peking Univ., China)
Pagepp. 332 - 337
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4B-4 (Time: 11:50 - 12:20)
TitleCache Capacity Aware Thread Scheduling for Irregular Memory Access on Many-Core GPGPUs
Author*Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou (National Chiao Tung Univ., Taiwan)
Pagepp. 338 - 343
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