| Title | Lithographic Defect Aware Placement Using Compact Standard Cells Without Inter-Cell Margin |
| Author | *Seongbo Shim, Yoojong Lee, Youngsoo Shin (KAIST, Republic of Korea) |
| Page | pp. 47 - 52 |
| Keyword | placement, lithography, PVB, defect |
| Abstract | Conventional standard cells contain extra space, called inter-cell margin, to prevent potential defects caused by lithography process. Margin is indeed necessary between some cell pairs, but there are also lots of cell pairs that do not yield any defects (or have very low probability of defects) when they are placed without margin. We address a new placement problem using standard cells without inter-cell margin. Placement should be done such that defect probability is made as small as possible while standard objectives such as wirelength is also pursued. The key in this approach is efficient computation of defect probabilities of all cell pairs and arranging them as a table that is referred to by a placer. We study how the cell pairs can be grouped by examining similar patterns along cell boundary, which greatly reduces the number of defect probability computation. The proposed placement method was evaluated on a few test circuits using 28-nm technology. Chip area was reduced by 10.8% on average with average and maximum defect probability kept below 0.4% and 4.1%, respectively. |
| Slides |
| Title | Structural Planning of 3D-IC Interconnects by Block Alignment |
| Author | *Johann Knechtel (Institute of Electromechanical and Electronic Design, Dresden University of Technology, Germany), Evangeline F. Y. Young (Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong), Jens Lienig (Institute of Electromechanical and Electronic Design, Dresden University of Technology, Germany) |
| Page | pp. 53 - 60 |
| Keyword | 3D-IC interconnect structures, block aligment, 3D floorplanning |
| Abstract | Three-dimensional integrated circuits rely on optimized interconnect structures for blocks which are spread among one or multiple dies. We demonstrate how 2D and 3D block alignment can be efficiently utilized for structural planning of different interconnects. To realize this, we extend the corner block list and provide effective techniques for 3D layout generation, i.e., block placement and alignment. Our techniques are made available in an open-source, simulated-annealing-based tool. Besides block alignment, it accounts for key objectives in 3D design like fast thermal management and fixed-outline floorplanning. Experimental results on GSRC and IBM-HB+ circuits demonstrate the capabilities of our tool for both planning 3D-IC interconnects by
block alignment and for 3D floorplanning in general. |
| Slides |
| Title | Comprehensive Die-Level Assessment of Design Rules and Layouts |
| Author | Rani Ghaida (GLOBALFOUNDRIES, U.S.A.), Yasmine Badr (University of California, Los Angeles, U.S.A.), Mukul Gupta (Qualcomm Inc., U.S.A.), Ning Jin (GLOBALFOUNDRIES, U.S.A.), *Puneet Gupta (University of California, Los Angeles, U.S.A.) |
| Page | pp. 61 - 66 |
| Keyword | Design Technology Co-optimization (DTCO), Design for Manufacturing (DFM), Design Rules, Layout, Technology |
| Abstract | Co-development of design rules and layout methodologies is the key to successful adoption of a technology. We develop the first framework for systematic evaluation of design rules and their interaction with layouts, performance, margins and yield at the chip-scale (as opposed to cell-level). A "good chips per wafer" metric is used to unify area, performance, variability and functional yield. For instance, a study of well-to-active spacing rule reveals a non-monotone dependence of rule value to chip area (although cell area relationship is monotone). |
| Slides |