| Title | Statistical Analysis of Random Telegraph Noise in Digital Circuits |
| Author | *Xiaoming Chen, Yu Wang (Tsinghua University, China), Yu Cao (Arizona State University, U.S.A.), Huazhong Yang (Tsinghua University, China) |
| Page | pp. 161 - 166 |
| Keyword | random telegraph noise, statistical analysis, reliability |
| Abstract | Random telegraph noise (RTN) has become an important
reliability issue at the sub-65nm technology node. Existing RTN simulation approaches mainly focus on single trap induced RTN and transient response of RTN, and they are usually time-consuming for circuit-level simulation. This paper proposes a statistical algorithm to study multiple traps induced RTN in digital circuits, to show the temporal distribution of circuit delay under RTN. Based on the simulation results we show how to protect circuit from RTN. Bias dependence of RTN is also discussed. |
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| Title | Semi-Analytical Current Source Modeling of FinFET Devices Operating in Near/Sub-Threshold Regime with Independent Gate Control and Considering Process Variation |
| Author | Tiansong Cui, Yanzhi Wang, Xue Lin, Shahin Nazarian, *Massoud Pedram (University of Southern California, U.S.A.) |
| Page | pp. 167 - 172 |
| Keyword | Current Source Modeling (CSM), FinFET circuits, near/sub-threshold, independent gate control, process variation |
| Abstract | FinFET has been proposed as an alternative for bulk CMOS. The characteristics of FinFETs operating in the near/sub-threshold region made it hard to verify the timing of a circuit using the conventional SSTA. In this paper, we extend the CSM to FinFET devices operating in multiple voltage regimes subject to independent gate control and process variations. |
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| Title | 2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling |
| Author | *Yukihide Kohira (The University of Aizu, Japan), Atsushi Takahashi (Tokyo Institute of Technology, Japan) |
| Page | pp. 173 - 178 |
| Keyword | Multi-domain clock skew scheduling, Two-domain clock skew schedule, 2-SAT |
| Abstract | Multi-domain clock skew scheduling is an effective technique to improve the performance of sequential circuits by using practical clock distribution network. Although the upper bound of performance of a circuit increases as the number of clock domains increases in multi-domain clock skew scheduling, the improvement of the performance becomes smaller while the cost of clock distribution network increases much. In this paper, a linear time algorithm that finds an optimum two-domain clock skew schedule is proposed. Experimental results show that optimum circuits are efficiently obtained by our method in short time. |
| Title | Power Minimization of Pipeline Architecture through 1-Cycle Error Correction and Voltage Scaling |
| Author | *Insup Shin (KAIST, Republic of Korea), Jae-Joon Kim (POSTECH, Republic of Korea), Youngsoo Shin (KAIST, Republic of Korea) |
| Page | pp. 179 - 184 |
| Keyword | timing speculation, low power design, error correction, voltage scaling |
| Abstract | We present a new 1-cycle timing error correction method, which allows aggressive voltage scaling in a pipelined architecture. The proposed method differs from the state-of-the-art in that the pipeline stage where the timing error occurs can continue to receive input data without halting to avoid data collision. The feature allows the pipeline to avoid recurring clock gating when timing errors happen at multiple stages or timing errors continue to occur at a certain stage. Compared to a state-of-art method, the proposed method shows 2-6% energy reduction for a 5-stage pipeline and 7-11% reduction for a 10-stage pipeline. In addition, the proposed logic to propagate clock gating signal is much simpler than that of the previous method by eliminating reverse propagation path of clock gating signal. |
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