| Title | Redundant-Via-Aware ECO Routing |
| Author | *Hsi-An Chien, Ting-Chi Wang (National Tsing Hua University, Taiwan) |
| Page | pp. 418 - 423 |
| Keyword | Redundant Via, ECO Routing |
| Abstract | Redundant via insertion (RVI) has become an inevitable means adopted in the routing or post-routing stage to enhance chip reliability and yield as feature size shrinks down to nanometer scale. The remaining routing resources, however, could become so limited after RVI, and make engineering change order (ECO) routing during a pre-mask stage or even a post-mask stage difficult to complete. In this paper, we study an ECO routing problem where redundant vias are present in the given layout but can be considered for replacement or removal to increase the routability and improve the routing quality. To find an ECO routing path, we construct only the necessary part of the routing graph on-the-fly, and develop an A* search based algorithm for achieving efficient path finding. We also take redundant via replacement, removal, and insertion into account when formulating the routing cost, and apply a state-of-the-art method to perform redundant via replacement and insertion. Experiments show that our algorithm not only successfully routes all test cases but also efficiently produces high-quality solutions. |
| Title | A Fast and Provably Bounded Failure Analysis of Memory Circuits in High Dimensions |
| Author | Wei Wu, Fang Gong (University of California, Los Angeles, U.S.A.), Gengsheng Chen (Fudan University, China), *Lei He (University of California, Los Angeles, U.S.A.) |
| Page | pp. 424 - 429 |
| Keyword | SRAM, Failure probability, Importance sampling, High dimensions |
| Abstract | Memory circuits demands extremely high integration density and reliability under process variations. The most challenging task is how to accurately estimate the extremely small failure probability of memory circuits where the circuit failure is a ``rare event''. Classic importance sampling has been widely recognized to be inaccurate and unreliable in high dimensions. To address this issue, we propose a fast statistical analysis to estimate the probability of rare events in high dimensions and prove that the estimation is always bounded. This methodology has been successfully applied to the failure analysis of memory circuits with hundreds of variables. Experiments on a 54-dimensional SRAM cell circuit show that the proposed approach achieves 1150X speedup over Monte Carlo without compromising any accuracy. It also outperforms the classification based method (e.g., Statistical Blockade) by 204X and existing importance sampling method (e.g., Spherical Sampling) by 5X. On another 90-dimension circuit, the proposed approach yields 364X speedup over Monte Carlo while existing importance sampling methods completely fail to provide reasonable accuracy. |
| Slides |
| Title | Predicting Circuit Aging Using Ring Oscillators |
| Author | Deepashree Sengupta, *Sachin Sapatnekar (University of Minnesota, U.S.A.) |
| Page | pp. 430 - 435 |
| Keyword | BTI, Ring oscillators, UofM model |
| Abstract | This paper presents a method for inferring circuit
delay shifts due to bias temperature instability using ring oscillator
(ROSC) sensors. This procedure is based on presilicon analysis,
postsilicon ROSC measurements, a new aging analysis model called
the Upperbound on f_Max (UofM), and a look-up table that stores
a precomputed degradation ratio that translates delay shifts in the
ROSC to those in the circuits. This method not only yields delay
estimates within 0:2% of the true values with very low runtime, but
is also independent of temperature and supply voltage variations. |
| Slides |
| Title | Statistical Analysis of Process Variation Based on Indirect Measurements for Electronic System Design |
| Author | *Ivan Ukhov, Mattias Villani, Petru Eles, Zebo Peng (Linköping University, Sweden) |
| Page | pp. 436 - 442 |
| Keyword | statistical analysis, process variation, Bayesian inference |
| Abstract | We present a framework for the analysis of process variation across semiconductor wafers. The framework is capable of quantifying the primary parameters affected by process variation, e.g., the effective channel length, which is in contrast with the former techniques wherein only secondary parameters were considered, e.g., the leakage current. Instead of taking direct measurements of the quantity of interest, we employ Bayesian inference to draw conclusions based on indirect observations, e.g., on temperature. |
| Slides |