| Title | Symbolic Computation of SNR for Variational Analysis of Sigma-Delta Modulator |
| Author | *Jiandong Cheng, Guoyong Shi (Shanghai Jiao Tong University, China) |
| Page | pp. 443 - 448 |
| Keyword | Sigma-delta modulator, Statistical analysis, Switched-capacitor, Symbolic analysis, Signal-to-noise ratio |
| Abstract | Signal-to-noise ratio (SNR) is an important design metric for
switched-capacitor sigma-delta modulators (SC-SDMs).
In an automatic synthesis environment, fast SNR computation is of paramount importance.
So far the main SNR computation method has been behavioral simulation.
Other less accurate methods are based on empirical formulas.
These methods could not contribute too much to enhancing synthesis efficiency.
In this work a highly efficient and purely symbolic SNR computation method
is proposed. The difficulty in the computation of noise power (requiring integration
of a rational function) is overcome by a Taylor polynomial approximation.
Together with a symbolic loop-transfer analysis tool, the SNR can be computed fully
symbolically. This novel computation method is applied for variational SC-SDM analysis.
The effectiveness and efficiency are compared to behavioral Monte Carlo simulation results. |
| Title | Sparse Statistical Model Inference for Analog Circuits under Process Variations |
| Author | *Yan Zhang, Sriram Sankaranarayanan, Fabio Somenzi (University of Colorado at Boulder, U.S.A.) |
| Page | pp. 449 - 454 |
| Keyword | Sparse regression, Statistical model inference, Analog verification |
| Abstract | In this paper, we address the problem of performance modeling for transistor-level circuits under process variations. A sparse regression technique is introduced to characterize the relationship between the process parameters and the output responses. This approach relies on repeated simulations to find polynomial approximations of response surfaces. It employs a heuristic to construct sparse polynomial expansions and a stepwise regression algorithm based on LASSO to find low degree polynomial approximations. The proposed technique is able to handle many tens of process parameters with a small number of simulations when compared to an earlier approach using ordinary least squares. We present our approach in the context of statistical model inference (SMI), a recently proposed statistical verification framework for transistor-level circuits. Our experimental evaluation compares percentage yields predicted by our approach with Monte-Carlo simulations and SMI using ordinary least squares on benchmarks with up to 30 process parameters. The sparse-SMI approach is shown to require significantly fewer simulations, achieving orders of magnitude improvement in the run times with small differences in the resulting yield estimates. |
| Slides |
| Title | Time-Domain Performance Bound Analysis for Analog and Interconnect Circuits Considering Process Variations |
| Author | *Tan Yu, Sheldon Tan (University of California, Riverside, U.S.A.), Yici Cai (Tsinghua University, China), Puying Tang (University of Electronic Science and Technology of China, China) |
| Page | pp. 455 - 460 |
| Keyword | Time-domain, bound analysis |
| Abstract | Time-Domain worst case or performance bound estimation for analog
integrated circuits and interconnect circuits are crucial for both
analog and digital circuit design and optimization in the presence
of process variations. In this paper, we present a novel
non-Monte-Carlo performance bound analysis technique in time domain.
The new method consists of several steps. First the symbolic
transient modified nodal analysis (MNA) formulation of the circuit
matrices of ( linearized) analog and interconnect circuits at a time
step is formed. Then the closed-form expressions of the interested
performance in terms of variational parameters of the circuit
matrices of ( linearized) analog and interconnect circuits are
derived via a graph-based symbolic analysis method. Then
time-domain performance response bound of current time step are
obtained by a nonlinear constrained optimization process subject to
the parameter variations and variational circuit state bounds
computed from the previous time step. The proposed method is more
amenable for computing high sigma bounds than standard MC method.
Experimental results show that the new method can delivers order of
magnitudes speedup over standard Monte Carlo simulation on some
typical analog circuits and interconnect circuits with very high
accuracy. |
| Slides |
| Title | A Robustness Optimization of SRAM Dynamic Stability by Sensitivity-Based Reachability Analysis |
| Author | Yang Song, *Sai Manoj P. D., Hao Yu (Nanyang Technological University, Singapore) |
| Page | pp. 461 - 466 |
| Keyword | Dynamic stability optimization, Reachability analysis, Large-signal sensitivity |
| Abstract | A robustness optimization of SRAM dynamic stability at nano-scale
is developed in this paper by zonotope-based reachability analysis.
A backward Euler method is developed to efficiently perform reachability analysis with zonotope
to deal with multiple device parameters with tuning ranges.
Moreover, a sensitivity calculation of zonotope is developed
to optimize safety distance by simultaneously tuning multiple SRAM device parameters without multiple repeated computations.
As such, sequential robustness optimizations can be performed such that the optimized SRAM designs
can depart from unsafe region but converge into safe region.
The proposed method is implemented inside a SPICE-like simulator.
As shown by numerical experiments,
the proposed method can achieve 600x speedup on an average
compared to the traditional verification method by Monte-Carlo under the similar accuracy.
In addition, compared to the traditional small-signal based sensitivity optimization,
our method can converge faster with high accuracy. |
| Slides |