| Title | Walking Pads: Fast Power-Supply Pad-Placement Optimization |
| Author | Ke Wang (University of Virginia, U.S.A.), *Brett Meyer (McGill University, Canada), Runjie Zhang, Kevin Skadron, Mircea Stan (University of Virginia, U.S.A.) |
| Page | pp. 537 - 543 |
| Keyword | multi-core, power delivery, C4 pad allocation, IR Drop, heuristic optimization |
| Abstract | We propose a novel C4 pad placement optimization framework for 2D power delivery grids: Walking Pads (WP). WP optimizes pad locations by moving pads according to the "virtual forces" exerted on them by other pads and current sources in the system. WP algorithms achieve the same IR drop as state-of-the-art techniques, but are up to 634X faster. We further propose an analytical model relating pad count and IR drop for determining the optimal pad count for a given IR drop budget. |
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| Title | Power Supply Noise-Aware Workload Assignments for Homogenous 3D MPSoCs with Thermal Consideration |
| Author | *Yuanqing Cheng (LIRMM, France), Aida Todri-Sanial (CNRS/LIRMM, France), Alberto Bosio (University of Montpellier/LIRMM, France), Luigi Dilillo, Patrick Girard (CNRS/LIRMM, France), Arnaud Virazel (University of Montpellier/LIRMM, France) |
| Page | pp. 544 - 549 |
| Keyword | 3D Homogeneous MPSoC, Workload Assignment, Power Supply Noise, Thermal |
| Abstract | In order to improve performance and reduce cost, multi-processor system on chip (MPSoC) is increasingly becoming attractive. At the same time, 3D integration emerges as a promising technology for high density integration. 3D homogenous MPSoCs combine the benefits of both. However, high current demand and large on-chip switching activity variations introduce severe power supply noise (PSN) for 3D MPSoCs, which can increase critical path delay, and degrade chip performance and reliability. Meanwhile, thermal gradient should also be considered for 3D MPSoCs to avoid generation of hotspot. In the paper, we investigate the PSN effects of different workloads and propose an effective PSN estimation method. Then, a heuristic workload assignment algorithm is proposed to suppress PSN under the given thermal constraint. The experimental results show that PSNs can be reduced significantly compared with thermal-balanced workload assignment scheme, and the system performance can be improved as well. |
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| Title | SwimmingLane: A Composite Approach to Mitigate Voltage Droop Effects in 3D Power Delivery Network |
| Author | *Xing Hu (Institute of Computing Technology, University of Chinese Academy of Sciences, China), Yi Xu (Space Science Institute, Macau University of Science and Technology, Macau/Advanced Micro Devices Research China Laboratory, China), Yu Hu (Institute of Computing Technology, University of Chinese Academy of Sciences, China), Yuan Xie (Advanced Micro Devices, China/Pennsylvania State University, U.S.A.) |
| Page | pp. 550 - 555 |
| Keyword | 3D chip, Voltage droop |
| Abstract | Despite the promising features of rapid data transferring across layers, low transmission power and high device density, 3D integration technology also presents many challenges, one of which is power integrity. By stacking multiple dies vertically, 3D chips have higher load than the same-sized 2D chips, leading to larger voltage droop and exacerbating damage to power integrity. To alleviate this problem, we first analyze the impact of application behaviors on voltage droop in a 3D power supply network (PDN) and observe that voltage droop is extremely imbalanced either across different layers or among the cores in the same layer. Then we propose a hardware and heuristic software co-design: (1) Mitigating the interference among different dies via a layer-independent scheme, and (2) balancing the intra-layer voltage droop and reducing the worst-case margin via OS scheduling. Compared to conventional designs, our schemes can reduce power consumption by 18%, worst-case voltage droops by 13%, and the number of voltage violations by 40%. |
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