Special Sessions

  • Date: January 24-26 2007
  • Place: Pacifico Yokohama, Room 416+417, 4F

Date/Time Title
1D Wednesday, January 24 / 10.15 - 12.20 Presentation + Poster Discussion:
University Design Contest
2D January 24 / 13.30 - 15.35 Invited Talks + Panel Discussion:
Design for Manufacturability
3D January 24 / 16.00 - 18.05 Invited Talks:
Embedded Software for Multiprocessor Systems-on-Chip
4D January 25 / 10.15 - 12.20 Invited Talks:
EDA Challenges for Analog/RF
7D January 26 / 10.15 - 12.20 Panel Disucssion:
Multi-Processor Platforms for Next Generation Embedded Systems

Wednesday, January 24, 10:15-12:20, 1D

"Presentation + Poster Discussion: University Design Contest"

Wednesday, January 24, 13:30-15:35, 2D

"Invited Talks + Panel Discussion: Design for Manufacturability"

  • 2D-1:
    Modeling Sub-90nm On-chip Variation for DFM
    - Kelvin Doong (TSMC, Taiwan)
  • 2D-2:
    DFM Reality in Sub-nanometer IC Design
    - Nishath Verghese (Clear Shape, United States)
  • 2D-3:
    DFM/DFY Practices during Physical Designs for Timing, Signal Integrity, and Power
    - Ke-Cheng Chu (Global Unichip, Taiwan)
  • 2D-4:
    Advanced Academic Researches Pertinent to DFM
    - Ting-Chi Wang (NTHU, Taiwan)
  • 2D-5:
    Panel Discussion
    Moderator: Keh-Jeng Chang (NTHU, Taiwan)
    Panelists: Kelvin Doong (TSMC, Taiwan)
    Nishath Verghese (Clear Shape, United States)
    Jiing-Yuan Lin (Global Unichip, Taiwan)
    Ting-Chi Wang (NTHU, Taiwan)
    Andrew Kahng (Blaze DFM, United States)

Wednesday, January 24, 16:00-18:05, 3D

"Invited Talks: Embedded Software for Multiprocessor Systems-on-Chip”

  • 3D-1:
    Model-based Framework of Embedded Software Design for MPSoC
    - Soonhoi Ha (SNU, Korea)
  • 3D-2:
    RTOS and Codesign Toolkit for Multiprocessor Systems-on-chip
    - Shinya Honda (Nagoya Univ., Japan)
  • 3D-3:
    Energy-efficient Real-time Task Scheduling in Multiprocessor DVS Systems
    - Jian-Jia Chen (National Taiwan Univ., Taiwan)
  • 3D-4:
    Towards Scalable and Secure Execution Platform for Embedded Systems
    - Junji Sakai (NEC, Japan)

Thursday, January 25, 10:15-12:20, 4D

"Invited Talks: EDA Challenges for Analog/RF”

  • 4D-1:
    Design tool solutions for mixed-signal/RF circuit design in CMOS
    - Georges Gielen (Katholieke Universiteit Leuven, Belgium)
  • 4D-2:
    Challenges to accuracy for the design of deep-submicron RF-CMOS circuits
    - Sadayuki Yoshitomi (Toshiba Co., Japan)
  • 4D-3:
    Advanced tools for simulation and design of oscillators/PLLs
    - Jaijeet Roychowdhury (Univ. of Minnesota)

Friday, January 26, 10:15-12:20, 7D

"Panel Discussion: Multi-Processor Platforms for Next Generation Embedded Systems”

Organizer: Nikil Dutt (Univ. of California, Irvine, United States)
Panelists: David Goodwin (Tensilica, United States)
Kazuyuki Hirata (ARM, Japan)
Peter Hofstee (IBM, United States)
Rudy Lauwereins (IMEC, Belgium)
Maurizio Paganini (STMicroelectronics, France)

Last Updated on: October 31, 2006