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Designers' Forum
Designers' Forum is a new program that shares design experience and solutions of real product designs of the industries. Its topics include SoC HW/SW verification, low-power SoC technologies, chip-to-chip signal solution and top 10 issues.
- Date: January 25-26, 2007
- Place: Pacifico Yokohama, Conference Center, Small Auditorium, 5F
- Designers' Forum Chair, Industry Liaison Chair: Haruyuki Tago (TOSHIBA CORPORATION)
- Designers' Forum Vice Chair: Kazutoshi Kobayashi (Kyoto University)
- Industry Liaison
| Date/Time | Title | ||
| 5D | January 25 / 13:30 - 15:35 | Panel Discussion : Presilicon SoC HW/SW Verification |
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| 6D | January 25 / 16:00 - 17:50 | Invited Talks: Low-power SoC Technologies |
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| 8D | January 26 / 13:30 - 15:35 | Invited Talks: High-speed Chip to Chip Signaling Solutions |
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| 9D | January 26 / 16:00 - 18:05 | Panel Discussion: Top 10 Design Issues |
5D : Thursday, January 25, 13:30-15:35, Small Auditorium, 5F
Panel Discussion : Presilicon SoC HW/SW Verification
Organizer: Tetsuji Sumioka (Sony, Japan)
Moderator: Tetsuji Sumioka (Sony, Japan)
Panelists: Jason Andrews (Cadence, United States),
Graham Hellestrand (VaST Systems Technology, United States),
Hidefumi Kurokawa (NEC Electronics, Japan),
Ilya Klebanov (Advanced Micro Devices, Canada),
Seiji Koino (Toshiba, Japan)
6D: Thursday, January 25, 16:00-17:50, Small Auditorium, 5F
Invited Talks: Low-power SoC Technologies
6D-1: Plenary Talk --Overview on Low Power SoC Design Technology--
Kimiyoshi Usami (Shibaura Inst. of Tech., Japan)
6D-2: The Development of Low-power and Real-time VC- 1/H.264/MPEG-4 Video Processing Hardware
Masaru Hase, Kazushi Akie, Masaki Nobori, Keisuke Matsumoto (Renesas, Japan)
6D-3: Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-media Engine SoC (S1G)
Koichi Mori, Masakazu Suzuki, Yasuo Ohara, Satoru Matsuo, Atsushi Asano (Toshiba, Japan)
6D-4: Low Power Techniques for Mobile Application SoCs based on Integrated Platform “UniPhier”
Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita (Matsushita Electric Industrial, Japan)
8D: Friday, January 26, 13:30-15:35, Small Auditorium, 5F
Invited Talks: High-speed Chip to Chip Signaling Solutions
8D-1: Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation
Atsushi Hiraishi, Toshio Sugano (Elpida Memory, Japan), Hideki Kusamitsu (Yamaichi Electronics)
8D-2:Xbox360TM Front Side Bus - A 21.6 Gb/s End to End Interface Design
David Siljenberg, Steve Baumgartner, Tim Buchholtz, Mark Maxson, Trevor Timpane (IBM, United States), Jeff Johnson (Cadence Design Systems, United States)
8D-3:Design Consideration of 6.25 Gbps Signaling for High-Performance Server
Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone (Fujitsu Laboratories of America, United States)
8D-4:System Co-design and Analysis Approach to Implementing the XDRTM Memory System of the Cell Processor Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production
Wai-Yeung Yip, Scott Best, Wendemagegnehu Beyene, Ralf Schmitt (Rambus, United States)
9D: Friday, January 26, 16:00-18:05, Small Auditorium, 5F
Panel Disussion: Top 10 Design Issues
Organizer: Haruyuki Tago (Toshiba, Japan)
Moderator: Peter Hofstee (IBM, United States)
Panelists: Toshihiro Hattori(Renesas Technology, Japan)
Tadahiro Kuroda (Keio University, Japan)
Toshinari Takayanagi (P.A., Semi, United States)
Toshinori Sato (Kyushu University, Japan)