Student Forum at ASP-DAC 2007

The Student Forum at ASP-DAC 2007 is a poster session for graduate students to present their research work. This is a great opportunity for students to get feedback and have discussion with people from academia and industry.

  • Date: January 25, 2007 (12:20-13:30)
  • Place: Pacifico Yokohama, 4F, Room 418


  • Hiroo Sekiya - Chiba University, Japan (IEICE Tokyo Section)
  • Toshiyuki Shibuya - Fujitsu Laboratories, Japan (IEICE Technical Group on VLSI Design Technologies)

Award Winners:

  • Best Poster Award
    ID:4, Kuang-Yao Lee,
    "Post-Routing Redundant Via Insertion and Line End Extension for Yield/Reliability Improvement"
  • Outstanding Achievement Award
    ID:5, Pei-Ci Wu,
    "Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction"
  • Young Student Award
    ID:7, Hiroki Matsutani,
    "Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network"

Paper ID Title Author Affiliates
1 Energy vs. Performance Trade-Offs and Interconnect-Aware Design for Coarse Grained Reconfigurable Processors Andy Lambrechts IMEC vzw, Belgium
3 A Low-Power, High-Performance 32 bit Conditional Sum Adder Shengxiang Fan Peking University, China
4 Post-Routing Redundant Via Insertion and Line End Extension for Yield/Reliability Improvement Kuang-Yao Lee National Tsing Hua University, Taiwan
5 Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction Pei-Ci Wu National Tsing Hua University, Taiwan
7 Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network Hiroki Matsutani Keio University, Japan
8 Design Methodology and CAD Tools for Nanometer FPGAs: Optimization for Leakage Power and Crosstalk Hassan Hassan University of Waterloo, Canada
9 Tailoring Circuit-Switched Network-on-Chip to Application-Specific SOC KUEI-CHUNG CHANG National Chung Cheng University, Taiwan
10 Low-Ripple-Voltage and High-Speed-Response Control System with MEMS Technology for Load Regulation of Switching Regulators Masashi Kono Gunma University, Japan
11 Wire Length Estimation for Block Placement Tan Yan The University of Kitakyushu, Japan
12 An Operation Chaining Method with Global Analysis and Complex Specialized Functional Units in Behavioral Synthesis Tsuyoshi Sadakata Kyushu University, Japan
14 Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures Ittetsu TANIGUCHI Osaka University, Japan
15 Nonuniform Sampling ADC Using Time-to-Digital Converter and its Signal Processing Kazuya Shimizu Gunma University, Japan
16 An Effective Pseudo-transient Algorithm and its Implementations for Finding DC Operating Points of Nonlinear Circuits Hong Yu Waseda University, Japan
17 A Data Alignment Method for Block Floating Point Systems Takashi Hamabe Osaka University, Japan
18 3D-Floorplanning by Practical MOVE Operation with smooth Solution Space Hidenori OHTA Tokyo University of Agriculture and Technology, Japan
19 An Effort toward Design Automation of General Synchronous Circuit Yousuke HARADA Tokyo Institute of Technology, Japan
21 An SoC Architecture of H.264/AVC Decoder with Block Pipelining Structure Sumek WISAYATAKSIN Tokyo Institute of Technology, Japan
22 A new design framework for multiprocessor system on chip Arif Ullah Khan Tokyo Institute of Technology, Japan

Committee Members

Hiroo Sekiya (Chiba University, Japan: IEICE Tokyo Section)
Toshiyuki Shibuya (Fujitsu Laboratories, Japan: IEICE TGVLD)

Poster Selection Committee Members:
Ali Afzali-Kusha (Tehran University, Iran)
Supratik Chakraborty (IIT Bombay, India)
Naehyuk Chang (Seoul National University, South Korea)
Sheqin Dong (Tsinghua University, China)
Toru Ishihara (Kyushu University, Japan)
Kazuhito Ito (Saitama University, Japan)
Philip Leong, (Chinese University of Hong Kong, Hong Kong)
Hiroshi Saito (Aizu University, Japan)
Omid Shoaei (University of Tehran, Iran)
Makoto Sugihara (Institute of Systems and Information Technologies, Japan)
Nozomu Togawa (Waseda University, Japan)

Student Representative:
Bakhtiar Affendi (Tokyo Institute of Technology, Japan)

Farzan Fallah (Fujitsu Labs. of America, USA)
Shinji Kimura (Waseda University, Japan)
Yoichi Shiraishi (Gunma University, Japan)

ASP-DAC liaison:
Atsushi Takahashi (Tokyo Institute of Technology, Japan: ASP-DAC2007 Secretary)

Hosted by :
IEICE Technical Group on VLSI Design Technologies (TGVLD)
IEICE Tokyo Section

Sponsored by :
ASP-DAC 2007
IEICE Engineering Sciences Society (ESS)
SpringSoft Foundation

Last Updated on: January 25, 2007