University LSI Design Contest

The University LSI Design Contest is a key event of ASP-DAC, which focuses on real chip designs in academia. The Design Contest Committee selected 18 designs for presentation, from which winners of design awards will be announced in the conference.

  • Date: Wedneday, January 24, 2007
  • Place: Pacifico Yokohama, Conference Center, 4F
    • Oral Presentation: Room416+417 (10:15-12:20)
    • Poster Presentation: Room 418 (12:20-13:30) (Light meals will be served.)
  • Co-Chairs: Makoto Nagata (Kobe Univ., Japan), Fumio Arakawa (Hitachi, Japan)
  • Design Contest Committee

Award Winners

Outstanding Design Award
1D-1: "A 1Tb/s 3W Inductive-Coupling Transceiver Chip"
Noriyuki Miura, Tadahiro Kuroda

Special Feature Award
1D-9: "Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique"
Roel Pantonial, Md. Ashfaquzzaman Khan, Naoto Miyamoto, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi

1D-13: "Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic"
Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu

Time Title
1D-1 10:15 - 10:20 A 1Tb/s 3W Inductive-Coupling Transceiver Chip
1D-2 10:20 - 10:25 22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors
1D-3 10:25 - 10:30 A 2.8-V Multibit Complex Bandpass Delta-Sigma AD Modulator in 0.18 umCMOS
1D-4 10:30 - 10:35 A Wideband CMOS LC-VCO Using Variable Inductor
1D-5 10:35 - 10:40 Design of Active Substrate Noise Canceller using Power Suplly di/dt Detector
1D-6 10:40 - 10:45 A 20 Gbps Scalable Load Balanced Birkhoffvon Neumann Symmetric TDM Switch IC with SERDES Interfaces
1D-7 10:45 - 10:50 Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation
1D-8 10:50 - 10:55 Pseudo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems
1D-9 10:55 - 11:00 Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique
1D-10 11:00 - 11:05 Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes
1D-11 11:05 - 11:10 A Highly Integrated 8 mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16 MHz SoC Platform
1D-12 11:10 - 11:15 Configurable AMBA On-Chip Real-Time Signal Tracer
1D-13 11:15 - 11:20 Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic
1D-14 11:20 - 11:25 A Multi-Drop Transmission-Line Interconnect in Si LSI
1D-15 11:25 - 11:30 A 10GHz/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology
1D-16 11:30 - 11:35 A 90nm 8x16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations
1D-17 11:35 - 11:40 A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI
1D-18 11:40 - 11:45 Low-Power High-Speed 180-nm CMOS Clock Drivers

Last Updated on: October 31, 2006