| Title | (Invited Paper) Three-Dimensional Integration Technology and Integrated Systems |
| Author | *Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka (Tohoku University, Japan) |
| Page | pp. 409 - 415 |
| Abstract | A new three-dimensional (3-D) integration technology by a self-assembly method is described. In addition, 3-D integrated systems such as 3-D microprocessor chip, 3-D shared memory chip, 3-D image processing chip and 3-D artificial retina chip are demonstrated. |
| Slides | |
| Title | (Invited Paper) A 3D Prototyping Chip based on a Wafer-level Stacking Technology |
| Author | *Nobuaki Miyakawa (Honda Research Institute, Japan) |
| Page | pp. 416 - 420 |
| Keyword | Stacking Technology, Wafer-to-Wafer, 8 inch wafer, Trial Manufacture of 3 layer Stacked |
| Abstract | A case study on 3D IC process, prototyping, and EDA design flow |
| Title | (Invited Paper) CAD Challenges for 3D ICs |
| Author | David Kung, *Ruchir Puri (IBM Corp., United States) |
| Page | pp. 421 - 422 |
| Abstract | A fundamental shift in the technology has occurred beyond 90nm CMOS where the interconnect resistance has been increasing significantly to cause a repeater explosion problem. This problem translates into not only significant area overhead but also power, as repeaters lose power to leakage. 3D technology has the potential of easing the challenge of repeater explosion. In order to exploit the full potential of 3D technology, new challenges in the area of physical design, thermal analysis, system level design and analysis need to be addressed. 3D interconnects have the potential of reducing critical paths delays significantly, which are typically between memory and the interfacing logic. New tools that consider thermally aware physical design implementations, most importantly at the architecture and SoC level are crucial to the success of 3D as thermal issues are exacerbated in 3D implementations. To justify the cost and complexity overhead of 3D technology, it is essential to study the benefit of 3D early in the design cycle. This requires strong linkage between architecture level analysis tools and 3D physical planning tools. Most of the advantages of 3D will be utilized with new system architectures and physical implementations. Therefore, the tools to aid 3D implementation must also operate at the higher level in addition to the 3D place and route algorithms that have been proposed in the literature before. In fact, the benefits from 3D place and route will be limited since current 2D designs do a fairly good job of optimizing the critical path distance. There is a very strong need for 3D architectural and physical planning tools that operate in the domain of thermal, physical, and performance analysis in order to yield an optimized system implementation in 3D technology. Most of the studies reporting huge benefits from 3D for wire length do not adequately consider the physical impact of vertical vias. It is crucial to consider the impact of vertical vias on the physical design of ICs, from area, latency, and thermal impact point of view. |
| Title | (Invited Paper) Addressing Thermal and Power Delivery Bottlenecks in 3D Circuits |
| Author | *Sachin S. Sapatnekar (University of Minnesota, United States) |
| Page | pp. 423 - 428 |
| Keyword | 3D integrated circuits, temperature, power grid, analysis, optimization |
| Abstract | The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared to a 2D design. This has ramifications on two critical issues: firstly, it means that more heat is generated per unit footprint, potentially leading to thermal problems, and secondly, more current must be supplied per package pin, leading to possible power delivery bottlenecks. This paper presents an overview of the challenges and solutions in the domain of addressing these two issues in 3D integrated circuits. |
| Slides | |
| Title | (Invited Paper) The Road to 3D EDA Tool Readiness |
| Author | *Charles Chiang, Subarna Sinha (Synopsys, United States) |
| Page | pp. 429 - 436 |
| Keyword | TSV |
| Abstract | The design, representation and optimization of 3D ICs will require changes to the current EDA tool suite. Modifications will be necessary in the data models as well as the analysis and optimization algorithms at various design stages. This talk will provide an in-depth summary of the changes needed at the various design stages to enable and support 3D IC design. |