Preparation Guide for Technical Paper Submission

Deadline

The submission deadlines are set based on Taiwan Standard Time (TST). TST goes ahead of most other local times. The deadline by local times is as follows:

  • July 13 15:00 @ San Jose
  • July 13 18:00 @ New York
  • July 13 23:00 @ London
  • July 14 00:00 @ Paris, Munich
  • July 14 03:30 @ New Delhi
  • July 14 06:00 @ Beijing, Taipei
  • July 14 07:00 @ Tokyo, Seoul
  • July 14 08:00 @ Sydney

Key Dates:

  • Deadline for submission: July 14 (Mon), 2008 (06:00, TST)
  • Notification of acceptance: September 26 (Fri), 2008
  • Deadline for final version: November 17 (Mon), 2008 (06:00, TST)

Instructions

In order to submit your paper, please follow the instructions below.

1) Paper preparation

  • Initial manuscripts should NOT include authors' names and their affiliations in order to perform a blind review. Authors' names, their affiliations and the contact person are requested when you submit your paper via the paper submission system.

  • The paper should be between 3 to 6 pages in length including all figures, tables and references. The technical expositions will be reviewed by specialists but should include an introduction for nonspecialists that describes the problem and achieved results, focusing on the important ideas and their significance.

  • Accepted file format is PDF only. No other formats will be accepted. You must make a pdf file which can be read by Acrobat Reader 5.0. Manuscripts should not include special fonts such as Asian fonts.

  • The paper for initial submission is to be formated like this (LaTex, LaTex2e). You can get the templates of initial sumission for (LaTex), (LaTex2e), and (MSWord).

2) Paper Submission

Requirement

  • All accepted papers should be presented at the conference.
  • Dual submission with other conferences is not allowed.

Remarks:

  • Papers will be accepted for publication as either of regular papers or short papers. The paper type ** cannot ** be chosen by authors when submitting papers.
  • Papers may need to be shortened after acceptance, depending on the paper type. The page limit for short papers will be four.
  • The page limit for regular papers is 6 pages. For the camera-ready version up to 2 extra pages (maximum 8 pages) are allowed with extra payment.
  • Any modification in authors' names including the order of the listed authors after submission deadline is not allowed except that TPC approves the modification.


Area of Interest:

Original, unpublished works on, but not limited to, the following areas are invited.

[1] System-Level Design Methodology :
System modeling, specification, language, design methodology, performance analysis, hardware-software co-design/co-simulation/co-verification, HW-SW interface synthesis, IP/platform-based design, etc.
[2] System Architecture and Optimization:
System-on-Chip and multi-processor SoC (MPSoC) architecture design, low power system design, network on chip, system communication architecture, memory architecture, application-specific instruction-set processor (ASIP) synthesis, virtual platforms, etc.
[3] Embedded and Real-Time Systems:
Embedded system design, real-time system design, OS, middleware, compilation techniques, memory/cache optimization, interfacing and software issues.
[4] High-Level/Behavioral/Logic Synthesis and Optimization:
High-Level/behavioral/RTL synthesis, technology-independent optimization, technology mapping, interaction between logic design and layout, sequential and asynchronous logic synthesis, resource scheduling, allocation, and synthesis.
[5] Validation and Verification for Behavioral/Logic Design:
Logic simulation, symbolic simulation, formal verification, equivalence checking, transaction-level/RTL and gate-level modeling and validation, assertion-based verification, coverage-analysis, constrained-random testbench generation.
[6] Physical Design (Routing):
Routing, repeater issues, interconnect optimization, interconnect planning, module generation, layout verification, post-placement layout and optimization, clock network design.
[7] Physical Design (Placement):
Placement, floorplanning, partitioning, hierarchical design, interaction between physical design and logic synthesis.
[8] Timing, Power, Thermal Analysis and Optimization:
Deterministic and statistical static timing analysis, statistical performance analysis and optimization, low power design, power and leakage analysis, power/ground and package analysis and optimization, thermal analysis, etc.
[9] Signal/power Integrity, Interconnect/Device/Circuit Modeling and Simulation:
Signal/power integrity, clock and bus analysis, interconnect and substrate modeling/extraction, package modeling, device modeling/simulation, circuit simulation, high-frequency and electromagnetic simulation of circuits, etc.
[10] Design for Manufacturability/Yield and Statistical Design:
DFM, DFY, CAD support for OPC and RET, variability analysis, yield analysis and optimization, reliability analysis, design for resilience and robustness, cell library design, design fabrics, etc..
[11] Test and Design for Testability:
Testable design, fault modeling, ATPG, BIST and DFT, memory test and repair, core and system test, delay test, analog and mixed signal test.
[12] Analog, RF and Mixed Signal Design and CAD:
Analog/RF synthesis, analog layout, verification and simulation techniques, noise analysis, mixed-signal design considerations.
[13] Emerging technologies and applications:
(i)   System-level design case studies for emerging applications: multimedia, consumer electronics, communication, networking, ubiquitous computing, biomedical applications, etc.
(ii)   Post CMOS technologies: nanotechnology, quantum, optical interconnect, 3D integration, probabilistic architecture, microfluidics, molecular, bioelectronics, etc., with emphasis on modeling, analysis, novel circuit/architecture, CAD tools, and design methodologies.

Inquiry

For more information, please contact: aspdac09papersee.nthu.edu.tw
 
Technical Program Chair
Ren-Song Tsay
 
Technical Program Vice Co-Chair
Shinji Kimura
 
Technical Program Committee Secretary
Jing-Jia Liou

Last Updated on: 5 29, 2008