Archive
Program at a glance
Keynote addresses
- Keynote I: Challenges to EDA System from the View Point of Processor Design and Technology Drivers
Mitsuo Saito [pdf:5.2MB] - Keynote II: Automated Synthesis and Verification of Embedded Systems: Wishful Thinking or Reality?
Wolfgang Rosenstiel [pdf:8MB]
Special sessions
- 2D: EDA Acceleration Using New Architectures
- 3D: Hardware Dependent Software for Multi- and Many-Core Embedded Systems
- 4D: Challenges in 3D Integrated Circuit Design
- 9D: Dependable VLSI: Device, Design and Architecture - How should they cooperate ? -
Designers' Forum
- 5D: Consumer SoC
- 6D: ESL Design Methods
- 7D: Analog/RF Circuit Designs
- 8D: Near-Future SoC Architectures - Can Dynamically Reconfigurable Processors be a Key Technology?
University LSI Design Contest
Technical Sessions
- 1A: On-Chip Communication Architectures
- 1B: Dealing with Thermal Issues
- 1C: Advances in Behavioral Synthesis
- 2A: MPSoC and IP Integration
- 2B: Power Analysis and Optimization
- 2C: Logic and Arithmetic Optimization
- 3A: System-Level Design of 3D Chips and Configurable Systems
- 3B: Advances in Timing Analysis and Modeling
- 4A: System Level Architectures
- 4B: Beyond Traditional Floorplanning and Placement
- 4C: Signal/Power Integrity and Simulation
- 5A: Energy-Aware System Level Design Methodology
- 5B: Design for Manufacturing and Reliability
- 5C: Analog, RF and Mixed-Signal CAD
- 6A: System Level Simulation and Modeling
- 6B: Chip and Package Routing Techniques
- 7A: Compilation Techniques for Embedded Systems
- 7B: Sequential Design Verification
- 7C: Scan Test Generation
- 8A: High-Level Design and Scheduling
- 8B: Emerging Design Methodologies and Applications
- 8C: Verification, Test, and Yield
- 9A: Memory Systems Simulation and Optimization
- 9B: Emerging Technologies