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The 14th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".
Technical Program:   SIMPLE version   DETAILED version with abstract    One Page (Not Separated) version
Author Index:   HERE

Session Schedule


Tuesday, January 20, 2009

ABCD
1K (Small Auditorium, 5F)
Opening and Keynote Session I
8:30 - 10:00
1A (Room 411+412)
On-Chip Communication Architectures
10:15 - 12:20
1B (Room 413)
Dealing with Thermal Issues
10:15 - 12:20
1C (Room 414+415)
Advances in Behavioral Synthesis
10:15 - 12:20
1D (Room 416+417)
University LSI Design Contest
10:15 - 12:20
2A (Room 411+412)
MPSoC and IP Integration
13:30 - 15:35
2B (Room 413)
Power Analysis and Optimization
13:30 - 15:35
2C (Room 414+415)
Logic and Arithmetic Optimization
13:30 - 15:35
2D (Room 416+417)
Special Session: EDA Acceleration Using New Architectures
13:30 - 15:35
3A (Room 411+412)
System-Level Design of 3D Chips and Configurable Systems
15:55 - 18:00
3B (Room 413)
Advances in Timing Analysis and Modeling
15:55 - 18:00
3D (Room 416+417)
Special Session: Hardware Dependent Software for Multi- and Many-Core Embedded Systems
15:55 - 18:00


Wednesday, January 21, 2009

ABCD
2K (Small Auditorium, 5F)
Keynote Session II
9:00 - 10:00
4A (Room 411+412)
System Level Architectures
10:15 - 12:20
4B (Room 413)
Beyond Traditional Floorplanning and Placement
10:15 - 12:20
4C (Room 414+415)
Signal/Power Integrity and Simulation
10:15 - 12:20
4D (Room 416+417)
Special Session: Challenges in 3D Integrated Circuit Design
10:15 - 12:20
5A (Room 411+412)
Energy-Aware System Level Design Methodology
13:30 - 15:35
5B (Room 413)
Design for Manufacturing and Reliability
13:30 - 15:35
5C (Room 414+415)
Analog, RF and Mixed-Signal CAD
13:30 - 15:35
5D (Room 416+417)
Designers' Forum: Consumer SoC
13:30 - 15:35
6A (Room 411+412)
System Level Simulation and Modeling
15:55 - 18:00
6B (Room 413)
Chip and Package Routing Techniques
15:55 - 18:00
6D (Room 416+417)
Designers' Forum: ESL Design Methods
15:55 - 18:00


Thursday, January 22, 2009

ABCD
3K (Small Auditorium, 5F)
Keynote Session III
9:00 - 10:00
7A (Room 411+412)
Compilation Techniques for Embedded Systems
10:15 - 12:20
7B (Room 413)
Sequential Design Verification
10:15 - 12:20
7C (Room 414+415)
Scan Test Generation
10:15 - 12:20
7D (Room 416+417)
Designers' Forum: Analog/RF Circuit Designs
10:15 - 12:20
8A (Room 411+412)
High-Level Design and Scheduling
13:30 - 15:35
8B (Room 413)
Emerging Design Methodologies and Applications
13:30 - 15:35
8C (Room 414+415)
Verification, Test, and Yield
13:30 - 15:35
8D (Room 416+417)
Designers' Forum: Near-Future SoC Architectures -- Can Dynamically Reconfigurable Processors be a Key Technology?
13:30 - 15:35
9A (Room 411+412)
Memory Systems Simulation and Optimization
15:55 - 18:00
9B (Room 413)
Emerging Technologies
15:55 - 18:00
9D (Room 416+417)
Special Session: Dependable VLSI: Device, Design and Architecture -- How should they cooperate ? --
15:55 - 18:00