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The 14th Asia and South Pacific Design Automation Conference

Session 8A  High-Level Design and Scheduling
Time: 13:30 - 15:35 Thursday, January 22, 2009
Location: Room 411+412
Chairs: Yuichi Nakamura (NEC Corp., Japan), Keishi Sakanushi (Osaka Univ., Japan)

8A-1 (Time: 13:30 - 13:55)
TitleImproving Scalability of Model-Checking for Minimizing Buffer Requirements of Synchronous Dataflow Graphs
AuthorNan Guan (Northeastern Univ., China), *Zonghua Gu (HKUST, China), Wang Yi (Uppsala Univ., Sweden), Ge Yu (Northeastern Univ., China)
Pagepp. 715 - 720
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8A-2 (Time: 13:55 - 14:20)
TitleA Reverse-Encoding-based on-chip AHB Bus Tracer for Efficient Circular Buffer Utilization
Author*Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Pagepp. 721 - 726
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8A-3 (Time: 14:20 - 14:45)
TitleAnalyzing and Optimizing Energy Efficiency of Algorithms on DVS Systems: a First Step towards Algorithmic Energy Minimization
Author*Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ., Japan)
Pagepp. 727 - 732
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8A-4 (Time: 14:45 - 15:10)
TitleNovel Task Migration Framework on Configurable Heterogeneous MPSoC Platforms
AuthorHao Shen, *Frédéric Pétrot (TIMA Lab., France)
Pagepp. 733 - 738
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