Designers' Forum

Designers' Forum is conceived as a unique program that shares the design experience and solutions of real product developments among LSI designers and EDA academia/developers. It consists of these four special sessions:

  • Date: January 21-22, 2009
  • Place: Pacifico Yokohama, Conference Center, 4F, Room 416+417
  • Designers' Forum Chair: Kunihiro Asada (Univ. of Tokyo)
  • Designers' Forum Chair: Kunio Uchiyama (Hitachi Ltd.)
  • Designers' Forum Vice Chair: Makoto Ikeda (Univ. of Tokyo)
  • Designers' Forum Vice Chair: Sumio Morioka (NEC Corp.)

Date/Time Title
5D January 21 / 13:30 - 15:35 Oral Session:
Consumer SoCs
6D January 21 / 15:55 - 18:00 Panel Discussion:
ESL Design Methods
7D January 22 / 10:15 - 12:20 Oral Session:
Analog/RF Circuit Designs
8D January 22 / 13:30 - 15:35 Panel Discussion:
Near-Future SoC Architectures

Designs will be presented focusing mainly on the design styles, problems and ways to tackle these. Panel discussions will also be held concerning the latest design problems. The following gives detailed information of each session:



Session 5D: Wednesday, January 21, 13:30-15:35, Room 416+417

Oral Session: Consumer SoCs

This session deals with real SoC design for consumer electronics devices. Three presentations will be given from Hitachi, Renesas and Panasonic. Hitachi will introduce a video codec design on heterogeneous multi-processor architecture. Renesas will show a dual-mode baseband processor on a 65nm process and Panasonic will present their SoC development strategy using the common SoC platform Uniphier.

  • 5D-1 : Development of Full-HD Multi-standard Video CODEC IP Based on Heterogeneous Multiprocessor Architecture
    - Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira (Hitachi Ltd., Japan), Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori (Renesas Technology Corp., Japan)
  • 5D-2 : A 65nm Dual-Mode Baseband and Multimedia Application Processor SoC with Advanced Power and Memory Management
    - Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka (Renesas Technology Corp., Japan)
  • 5D-3 : UniPhier: Series Development and SoC Management
    - Yoshito Nishimichi, Nobuo Higaki, Masataka Osaka, Seiji Horii, Hisato Yoshida (Panasonic Corp., Japan)

Session 6D: Wednesday, January 21, 15:55-18:00, Room 416+417

Panel Discussion: ESL Design Methods

Panelists from LSI design companies, tool venders and academic institute will discuss about the latest ESL (Electronic System Level) design methodologies/tools and their use in practical SoC designs. Panelists will introduce tool flow and LSI design experiences using UML, MATLAB, SystemC and other high abstraction level modeling languages and tools.

Moderator: Takashi Hasegawa (Fujitsu Microelectronics Ltd., Japan)
Panelists: Simon Bloch (Mentor Graphics Corp., United States)
Ahmed Jerraya (CEA-LETI, France)
Gabriela Nicolescu (Ecole Polytechnique de Montreal, Canada)
Shigeru Oho (Hitachi, Ltd., Japan)
Koichiro Yamashita (Fujitsu Labs. Ltd., Japan)

Session 7D: Thursday, January 22, 10:15-12:20, Room 416+417

Oral Session: Analog/RF Circuit Designs

Four presentations on practical design of analog circuits will be given by Hitachi, Toshiba, Panasonic and NTT. Hitachi will introduce a spread spectrum clock generator for the serial ATA interface. Toshiba will show an RF circuit design in scaled SoC. Panasonic will introduce a strategic optimization method for pipeline and delta-sigma ADC. NTT will show a body area network.

  • 7D-1 : Design Methods for Pipeline & Delta-Sigma A-to-D converters with convex optimization
    - Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho (Panasonic Corp., Japan)
  • 7D-2 : A Low-Jitter 1.5-GHz and Large-EMI reduction 10-dBm Spread-Spectrum Clock Generator for Serial-ATA
    - Takashi Kawamoto, Masaru Kokubo (Hitachi Ltd., Japan)
  • 7D-3 : RF-Analog Circuit Design in Scaled SoC
    - Nobuyuki Itoh, Mototsugu Hamada (Toshiba Corp., Japan)
  • 7D-4 : An Approach to the RF-LSI Design for Ubiquitous Communication Appliances
    - Yuichi Kado, Mitsuru Harada (NTT, Japan)

Session 8D: Thursday, January 22, 13:30-15:35, Room 416+417

Panel Discussion: Near-Future SoC Architectures - Can Dynamically Reconfigurable Processors be a Key Technology?

Panelists from Hitachi, Toshiba, Panasonic Europe, Fujitsu and NEC will discuss the latest dynamic reconfigurable processor technologies, their practical use in consumer electronics devices, and their future expansion.

Moderator: Hideharu Amano (Keio Univ., Japan)
Panelists: Toru Awashima (NEC, Japan)
Hisanori Fujisawa (Fujitsu Labs. Ltd., Japan)
Naohiko Irie (Hitachi Ltd., Japan)
Takashi Miyamori (Toshiba Corp., Japan)
Tony Stansfield (Panasonic Europe Ltd., Great Britain)

Last Updated on: 10 30, 2008