Tutorials

  • Date: Monday, January 19, 2009 (9:30 - 17:00)
  • Place: Pacifico Yokohama, Conference Center, 4F
Time Title
Tutorial 1 (Full Day) 9:30 - 17:00 Software Development and Programming of Multicore LSI
Tutorial 2 (Half Day) 9:30 - 12:30 Formal Methods for C-Based Embedded System Design Verification
Tutorial 3 (Half Day) 9:30 - 12:30 Statistical Design on the Verge of Maturity: Revisiting the Foundation
Tutorial 4 and 5 (Two Half Days) 9:30 - 12:30, 14:00 - 17:00 Circuit Reliability: Modeling, Simulation, and Resilient Design Solutions
Tutorial 6 (Half Day) 14:00 - 17:00 Recent Advances in Low-Leakage VLSI Design
Tutorial 7 (Half Day) 14:00 - 17:00 Memory Architectures and Software Transformations for System Level Design

Tutorial 1 (FULL DAY), Monday, January 19, 9:30 - 17:00, Room 411+412

Software Development and Programming of Multicore LSI

Organizer:
Ahmed Amine Jerraya (TIMA, France)
Speakers:
Wayne Wolf (Georgia Institute of Technology, United States)
Damir Jamsek (IBM, United States)
Hiroyuki Tomiyama (Nagoya University, Japan)
Fabien Clermidy (CEA-LETI, France)

LSI designs integrate an increasing number of heterogeneous programmable units (CPU, ASIP and DSP subsystems) and sophisticated communication interconnects. In conventional computers programming is based on an operating system that fully hide the underlying hardware architecture. Unlike classic computers, the design of LSI includes the building of application specific memory architecture and specific interconnect and other kinds of hardware components required to efficiently executing the software for a well defined class of applications. In this case, the programming model hides both hardware and software interfaces that may include sophisticated communication and synchronization concepts to handle parallel programs running on the processors. When the processors are heterogeneous, multiple software stacks may be required. Additionally, when specific Hardware peripherals are used, the development of Hardware dependent Software (HdS) requires a long, fastidious and error prone development and debug cycle. This full day tutorial deals with challenges and opportunities for the programming of such complex devices.

  • Prof. Wayne Wolf will introduce and survey principles for the programming of multicore LSI.
  • Dr. Damir Jamsek will detail How to accelerate CAD applications with CUDA programming environment.
  • Prof. Hiroyuki Tomiyama will introduce and survey principles for RTOS (real-time operating systems) for multicore LSI.
  • Dr. Fabien Clermidy will explore programming future LSI based on Network on Chip.

Tutorial 2 (HALF DAY), Monday, January 19, 9:30 - 12:30, Room 413

Formal Methods for C-Based Embedded System Design Verification - Technical Trends and Practical Aspects -

Organizer:
Masahiro Fujita (University of Tokyo, Japan)
Speakers:
Masahiro Fujita (University of Tokyo, Japan)
Alan J. Hu (University of British Columbia, Canada)
Andy Chou (Coverity Inc., United States)

Recently there has been significant progress in formal analysis on C/C++ programs. New bugs in Linux kernels, which have several million lines of codes, have been found by formal analysis methods. In embedded system designs, C-based hardware designs are becoming common, and the techniques developed for C/C++ are expected to be applied to hardware design descriptions as well. There are basically three approaches to the verification problem: static analysis based on local traces of the descriptions, model checking with automatic abstraction/reduction of the descriptions, and equivalence checking with efficient identification of the differences between the descriptions. With appropriate usages, all of the three approaches give practical values to designers, and large and real-life design descriptions could be formally analyzed. The point here is how and where the formal methods are applied. Concentrating on their practical aspects, this tutorial gives the state-of-the-art formal methods and implemented tools for C based design descriptions. The tutorial has the following presentations:

  • Prof. Masahiro Fujita gives an overview of the three approaches for the formal analysis of C-based design descriptions.
  • Dr. Andy Chou presents various static checking methods and implemented tools with their applications to real life C descriptions.
  • Prof. Alan J. Hu presents model checking based formal verification of C-based design descriptions with various efficiency increasing techniques
  • Prof. Masahiro Fujita describes formal equivalence checking methods and implemented tools targeting designs under typical system level design flows.

Tutorial 3 (HALF DAY), Monday, January 19, 9:30 - 12:30, Room 414+415

Statistical Design on the Verge of Maturity: Revisiting the Foundation

Organizer:
Michael Orshansky (University of Texas, Austin, United States)
Speakers:
Sani Nassif (IBM, United States)
Michael Orshansky (University of Texas, Austin, United States)

Statistical analysis and design (optimization) methods have been actively researched over the last five years with hundreds of papers published on the subject. Many novel concepts and models have been presented, and alternative algorithms for SSTA and optimization developed. In this tutorial, we will re-assess the status of statistical analysis and design methodologies; evaluate evidence for its practical use, and point out the limitations of some of the assumptions made in the early years of the discipline.

Physical sources of variability:
This tutorial will review the latest sets of variability data collected from state-of-the-art production lines. The validity of some key assumptions often made about data is specifically reviewed:
  • Relative amount of variations inter-chip and intra-chip
  • Relative amounts of systematic/spatial and truly random variations
  • Designer control of variations, i.e. dependence of variation on device geometry and circuit structure
  • Methods for reducing the impact of variability, regularity for intra-chip, and adaptation for inter-chip
Statistical timing analysis methods:
The state-of-the-art SSTA methods and the patterns of their adoption in industry will be presented. Specifically, this tutorial will describe the use of SSTA as a multi-corner robustness checker.
Statistical/robust optimization:
This tutorial will revisit the state of the art in statistical optimization methods for timing and power yield.

Tutorials 4 and 5 (TWO HALF DAYs, morning and afternoon), Monday, January 19, 9:30 - 12:30, Room 416+417, Monday, January 19, 14:00 - 17:00, Room 416+417

Circuit Reliability: Modeling, Simulation, and Resilient Design Solutions
Section I (morning): Reliability Mechanisms and the Impact on IC Designs
Section II (afternoon): Circuit Aging Prediction and Resilient Design

Organizer:
Yu (Kevin) Cao (Arizona State University, United States)
Section I Speakers:
Yu (Kevin) Cao (Arizona State University, United States)
Kaushik Roy (Purdue University, United States)
Section II Speakers:
Marek Patyra (Intel, United States)
Subhasish Mitra (Stanford University, United States)

The aggressive scaling of CMOS technology to sub-45nm nodes has inevitably leads to multiple reliability concerns, such as negative-bias-temperature-instability (NBTI), soft errors, and time-dependent-dielectric-breakdown (TDDB). These effects manifest themselves as the temporal degradation of transistor parameters, profoundly affecting all aspects of circuit performance. While traditional research in this area has focused only on technology improvement, ignoring these effects in the design process causes an excessive amount of over-margining. As these reliability concerns become much more severe with continuous scaling, it is critical to understand, simulate, and adaptively mitigate their impact during the design stage.

In this context, this tutorial will present basic and more advanced topics on reliability modeling, simulation, and design solutions, including two sections:

Section I: Reliability Mechanisms and the Impact on IC Design
  • The underlying reliability mechanisms
  • Compact modeling and analysis techniques of circuit aging
  • Circuit design for reliability in both logic and memory circuits
Section II: Circuit Aging Prediction and Resilient Design
  • Circuit reliability analysis and prediction
  • Test and validation for circuit and product reliability
  • Latest design practices for resilience

This tutorial will conclude with a discussion on future reliability challenges, helping shed light on the need of resilient design techniques and tools.

Tutorial 6 (HALF DAY), Monday, January 19, 14:00 - 17:00, Room 414+415

Recent Advances in Low-Leakage VLSI Design

Organizer:
Youngsoo Shin (KAIST, Korea)
Speakers:
Youngsoo Shin (KAIST, Korea)
Kaushik Roy (Purdue University, United States)

This tutorial will discuss recent advances for designing low-leakage VLSI circuits, as well as challenges and opportunities for future research and development. The main focus will be on cell-based semi-custom design, where considering the interaction with other tools in standard design flow when new scheme is adopted is very important. The tutorial will start from leakage estimation considering process variations, which is important to further optimization and design planning. The next part of the tutorial will be minimizing leakage when circuit is in active, or in very short idle. Conventional multiple threshold voltage technique will be discussed, but recent advances in the area of sequential circuit design will be a focus. This includes the use of flip-flops of multiple gate-length and mixed threshold voltages, and adopting clock skew scheduling for further reducing leakage of sequential circuits. We will then go on to discuss fast power-gating circuits, including zigzag power-gating, multiple sleep modes, etc. Run-time power-gating will be discussed as well. In the third part of the tutorial, we will address several circuit techniques for reducing standby leakage. This includes standard power-gating, adaptive body-bias, dynamic voltage scaling, and combination of these. Again, the main focus will be on recent advances in these circuit techniques and how to employ these circuits in cell-based semi-custom design.

Tutorial 7 (HALF DAY), Monday, January 19, 14:00 - 17:00, Room 413

Memory Architectures and Software Transformations for System Level Design

Organizer:
Nikil Dutt (University of California, Irvine, United States)
Speakers:
Stylianos Mamagkakis (IMEC, Belgium)
Preeti Panda (Indian Institute of Technology, Delhi, India)

Memories continue to dominate the cost, performance and power of LSI designs. As we move towards sub-nanometer technologies, memories are also susceptible to soft-errors and thus affect the reliability of LSI designs. Traditionally memory issues are considered at a late stage in a system-level design flow, often resulting in designs that do not meet performance and/or power budgets, and with unnecessarily large memory footprints for the LSI designs. A memory-aware system level design flow can address these problems by customizing both the underlying memory architectures/organizations, as well as by transforming the system-level source code to generate an input for system-level design that is better tuned to the memory architectures and organizations. Such a "memory-aware" system level design flow can result in LSI designs exhibiting superior performance, power and memory footprint characteristics. This half-day tutorial will survey emerging memory architectural platforms and organizations, as well as software transformations that enable tuning of system-level applications to exploit the underlying memory organizations and architectures to improve performance, power and code size. Case studies on industrial LSI designs will demonstrate the efficacy of these approaches.

  • Prof. Preeti Panda will survey traditional and emerging memory architectures and organizations, including caches, scratchpad memories, buffers, and describe possible ways to exploit them.
  • Dr. Stylianos Mamagkakis will present CleanC, a set of techniques and tools that enable source code level parallelization and memory hierarchy/data reuse exploration techniques/tools.
Last Updated on: 10 17, 2008