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The 15th Asia and South Pacific Design Automation Conference

Session 10A  DFM3: Robust Design
Time: 15:30 - 17:10 Thursday, January 21, 2010
Location: Room 101A
Chairs: Toshiyuki Shibuya (Fujitsu Laboratories of America, Inc, U.S.A.), Yi Chang Lu (National Taiwan Univ., Taiwan)

10A-1 (Time: 15:30 - 15:55)
TitleSlack Redistribution for Graceful Degradation Under Voltage Overscaling
AuthorAndrew B. Kahng, *Seokhyeong Kang (UC San Diego, U.S.A.), Rakesh Kumar, John Sartori (UIUC, U.S.A.)
Pagepp. 825 - 831
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10A-2 (Time: 15:55 - 16:20)
TitleA Decoder-Based Switch Box to Mitigate Soft Errors in SRAM-Based FPGAs
Author*Hassan Ebrahimi, Morteza Zamani, HamidReza Zarandi (Amirkabir, Iran)
Pagepp. 832 - 837
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10A-3s (Time: 16:20 - 16:32)
TitleOn Process-Aware 1-D Standard Cell Design
AuthorHongbo Zhang, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Kai-Yuan Chao (Intel Corp., U.S.A.)
Pagepp. 838 - 842
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10A-4s (Time: 16:32 - 16:44)
TitleD-A Converter Based Variation Analysis for Analog Layout Design
Author*Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Pagepp. 843 - 848
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