| Title | A Fast Symbolic Computation Approach to Statistical Analysis of Mesh Networks with Multiple Sources |
| Author | *Zhigang Hao, Guoyong Shi (Shanghai Jiaotong University, China) |
| Page | pp. 383 - 388 |
| Keyword | mesh, symbolic, moment, sensitivity, multiple sources |
| Abstract | Mesh circuits typically consist of many resistive links and many sources. Accurate analysis of massive mesh networks is demanding in the current integrated circuit design practice, yet their computation confronts numerous challenges. When variation is considered, mesh analysis becomes a much harder task. This paper proposes a symbolic computation technique that can be applied to the moment-based analysis of mesh networks with multiple sources. The variation issues are easily taken care of by a structured computation mechanism, which can naturally facilitate sensitivity based analysis. Applications are addressed by applying the computation technique to a set of mesh circuits with varying sizes. |
| Slides |
| Title | Minimizing Clock Latency Range in Robust Clock Tree Synthesis |
| Author | *Wen-Hao Liu, Yih-Lang Li, Hui-chi Chen (National Chiao Tung University, Taiwan) |
| Page | pp. 389 - 394 |
| Keyword | Clock Tree Routing, Buffer Insertion, Wire sizing, Zero skew, Clock Latency Range |
| Abstract | In the ISPD’09 Clock Network Synthesis (CNS) Contest, clock latency range (CLR) was initially minimized across multiple supply voltages under capacitance and slew constraints. CLR approximates the summation of the clock skew and the maximum source-to-sink delay variation for multiple supply voltages. This work develops an efficient three-stage clock tree synthesis flow for CLR minimization. Experimental results reveal that the proposed can yield less CLR than the top three winners of ISPD’09 CNS contest by 59%, 52.7% and 35.4% respectively. |
| Slides |
| Title | Blockage-Avoiding Buffered Clock-Tree Synthesis for Clock Latency-Range and Skew Minimization |
| Author | *Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang (Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan) |
| Page | pp. 395 - 400 |
| Keyword | Clock Tree Synthesis, Buffer Insertion, Skew and Slew Rate, Process Variation, Clock Latency Range |
| Abstract | In high-performance nanometer synchronous chip design, a buffered
clock tree with high tolerance of process variations is essential.
The nominal clock skew always plays a crucial role in determining
circuit performance and thus should be a first-order objective for
clock-tree synthesis. The clock latency range (CLR), which is the
latency difference under different supply voltages, is defined by
the 2009 ACM ISPD Clock Network Synthesis Contest as the major
optimization objective to measure the effects of process variation
on clock-tree synthesis. In this paper, we propose a three-level
framework which effectively constructs clock trees by performing
blockage-avoiding buffer insertion with both nominal skew and CLR
minimization. To cope with the objectives, we present a novel
three-stage TTR clock-tree construction algorithm which consists
of clock-tree Topology Generation, Tapping-Point Determination,
and Routing. Experimental results show that our framework with the
TTR algorithm achieves the best average quality for both nominal
skew and CLR, compared to all the participating teams for the 2009
ISPD Clock Network Synthesis Contest. |
| Slides |