| Title | Improved Weight Assignment for Logic Switching Activity During At-Speed Test Pattern Generation |
| Author | *Meng-Fan Wu, Hsin-Chieh Pan, Teng-Han Wang, Jiun-Lang Huang (National Taiwan University, Taiwan), Kun-Han Tsai, Wu-Tung Cheng (Mentor Graphics Corporation, U.S.A.) |
| Page | pp. 493 - 498 |
| Keyword | at-speed testing, IR-drop, weighted switching activity |
| Abstract | For two-pattern at-speed scan testing, the excessive power
supply noise at the launch cycle may cause the circuit under
test to malfunction, leading to yield loss. This paper
proposes a new weight assignment scheme for logic switching
activity; it enhances the IR-drop assessment capability
of the existing weighted switching activity (WSA) model.
By including the power grid network structure information,
the proposed weight assignment better reflects the regional
IR-drop impact of each switching event. For ATPG, such
comprehensive information is crucial in determining whether
a switching event burdens the IR-drop effect. Simulation results
show that, compared with previous weight assignment
schemes, the estimated regional IR-drop profiles better correlate
with those generated by commercial tools. |
| Slides |
| Title | Graph Partition based Path Selection for Testing of Small Delay Defects |
| Author | Zijian He, *Tao Lv, Huawei Li, Xiaowei Li (Institute of Computing Technology, CAS, China) |
| Page | pp. 499 - 504 |
| Keyword | SDD, delay testing, graph partition, Monte Carlo |
| Abstract | Critical path selection plays an important role in testing of small delay defects (SDDs). For some timing-balanced circuits, the numbers of candidate critical paths may be very large, and this will make Monte Carlo simulation based statistical timing analysis very inefficient. A fast path selection approach based on graph partition is proposed in this paper. First, a critical path graph (CPG) is generated to implicitly enumerate almost all candidate critical paths, and then the CPG is partitioned into several sub graphs which contain limited numbers of paths using two graph partition approaches. After that, Monte Carlo simulation is applied on each sub graph for path selection. At last, according to the partition topology of the CPG and path sets selected from each sub graph, a path set for the original CPG is generated using Union and Cartesian product operations for testing SDDs. Experimental results show that for circuits containing large numbers of candidate critical paths, the proposed path selection approach can reduce the CPU time significantly and maintain a high probability of capturing delay failures compared to path selection methods based on general Monte Carlo simulation. |
| Slides |
| Title | Emulating and Diagnosing IR-Drop by Using Dynamic SDF |
| Author | Ke Peng (University of Connecticut, U.S.A.), Yu Huang, Ruifeng Guo, *Wu-Tung Cheng (Mentor Graphics, U.S.A.), Mohammad Tehranipoor (University of Connecticut, U.S.A.) |
| Page | pp. 511 - 516 |
| Keyword | IR-drop defect, diagnosis, dynamic SDF |
| Abstract | The SDF (Standard Delay Format) information is very important in timing-aware simulation of VLSI designs. However, conventionally, SDF is only design dependent, but pattern independent, which is called static SDF in this paper. Static SDF ignores all dynamic pattern dependent parameters, such as IR-drop and crosstalk etc. In this paper, we propose a novel pattern dependent SDF, which is called dynamic SDF and we apply this technique to take IR-drop effects into consideration. With the proposed IR-drop-aware SDF files, we can improve the accuracy of simulation. We also do diagnosis on the failed patterns with the IR-drop-aware SDF files and pin point the pattern-dependent IR-drop defects in the design. Experimental results demonstrate the efficiency of this method. |
| Slides |