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The 15th Asia and South Pacific Design Automation Conference

Session 7D  Special Session: Dependable Silicon Design with Unreliable Components
Time: 8:30 - 10:10 Thursday, January 21, 2010
Location: Room 101D
Organizer & Moderator: Vincent Mooney (Georgia Tech/Nanyang Technological Univ., U.S.A.)

7D-1 (Time: 8:30 - 8:55)
Title(Invited Paper) Resilient Design in Scaled CMOS for Energy Efficiency
AuthorJames Tschanz, Keith Bowman, Muhammad Khellah, Chris Wilkerson, Bibiche Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, *Vivek K. De (Intel Corp., U.S.A.)
Pagep. 625
Detailed information (abstract, keywords, etc)
Slides

7D-2 (Time: 8:55 - 9:20)
Title(Invited Paper) Benefits and Barriers to Probabilistic Design
Author*Siva Narendra (Tyfone, Inc./Portland State Univ., U.S.A.)
Pagepp. 626 - 627
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7D-3 (Time: 9:20 - 9:45)
Title(Invited Paper) A Probabilistic Boolean Logic for Energy Efficient Circuit and System Design
AuthorLakshmi N. B. Chakrapani (Rice Univ., U.S.A.), *Krishna Palem (Rice Univ./Nanyang Technological Univ., U.S.A.)
Pagepp. 628 - 635
Detailed information (abstract, keywords, etc)

7D-4 (Time: 9:45 - 10:10)
Title(Panel Discussion) Dependable Silicon Design with Unreliable Components
AuthorOrganizer & Moderator: Vincent Mooney (Georgia Tech/Nanyang Technological Univ., U.S.A.), Panelists: Vivek K. De (Intel Corp., U.S.A.), Siva Narendra (Tyfone, Inc., U.S.A.), Krishna Palem (Rice Univ./Nanyang Technological Univ., U.S.A.)
Detailed information (abstract, keywords, etc)