| Title | A New Graph-theoretic, Multi-objective Layout Decomposition Framework for Double Patterning Lithography |
| Author | *Jae-Seok Yang (University of Texas at Austin, U.S.A.), Katrina Lu (Intel, U.S.A.), MinSik Cho (IBM Research, U.S.A.), Kun Yuan, David Z. Pan (University of Texas at Austin, U.S.A.) |
| Page | pp. 637 - 644 |
| Keyword | Double patterning lithography, Decomposition, Overlay, Balanced density, min-cut partitioning |
| Abstract | As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this paper, we propose a multi-objective min-cut based decomposition framework for stitch minimization, balanced density, and overlay compensation, simultaneously. The key challenge of DPL is to accomplish high quality decomposition for large-scale layouts under reasonable runtime with the following objectives: a) the number of stitches is minimized, b) the balance between two decomposed layers is maximized for further enhanced patterning, c) the impact of overlay on coupling capacitance is reduced for less timing variation. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. An additional decomposition constraints for self-overlay compensation are obtained by integer linear programming(ILP). With the constraints, global decomposition is executed by our modified FM graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures. |
| Slides |
| Title | A Robust Pixel-Based RET Optimization Algorithm Independent of Initial Conditions |
| Author | *Jinyu Zhang (Institute of Microelectronics, Tsinghua University, China), Min-Chun Tsai (Brion Technology, U.S.A.), Wei Xiong, Yan Wang, Zhiping Yu (Institute of Microelectronics, Tsinghua University, China) |
| Page | pp. 645 - 650 |
| Keyword | lithography, ILT, optimization, Initial condition |
| Abstract | A robust pixel-based optimization algorithm is proposed for mask synthesis of inverse lithography technology (ILT) to improve the resolution and pattern fidelity in optical lithography. Result shows that the final image fidelity is almost independent of the initial condition. To demonstrate the robustness of the algorithm, six typical desired mask patterns and two mask technologies are applied in mask synthesis optimization using 100 randomly generated initial conditions. The critical dimension (CD) is 60nm and the partial-coherence image system is applied. It is found that the final edge placement error (EPE) and iteration number are quite weakly dependent on the initial conditions. Good final image fidelity can be acquired using arbitrary initial conditions. This algorithm is about several orders of magnitude faster and more effective than other gradient-based algorithm and simulated annealing algorithm. |
| Title | A New Method to Improve Accuracy of Parasitics Extraction Considering Sub-wavelength Lithography Effects |
| Author | *Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu (National Taiwan University, Taiwan) |
| Page | pp. 651 - 656 |
| Keyword | Lithography, proximity effect, resolution enhancement technique, parasitics extraction, layout parameter extraction |
| Abstract | Modern nanometer integrated circuits are patterned by sub-wavelength lithography with significant shape deviation from drawn layouts. Full-chip parasitics extraction faces new challenges since shape distortions such as line end rounding and corner rounding cannot be accurately characterized by existing layout parameter extraction (LPE) techniques which assume perfect polygons. A new LPE method and efficient shape ap-proximation algorithms are proposed to account for the shape distortions. Preliminary results verified by field solver simulations indicate that accuracy of parasitics extraction can be significantly improved. |
| Slides |
| Title | Dead Via Minimization by Simultaneous Routing and Redundant Via Insertion |
| Author | *Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li (National Chiao Tung University, Taiwan) |
| Page | pp. 657 - 662 |
| Keyword | redundant via, track assignment, detailed routing |
| Abstract | While via failure significantly contributes to yield loss during manufacturing, post-routing redundant via insertion method is the conventional means of reducing the via failure rate, but only alive vias can be protected. As existing dead vias still lower manufacturing yield, identifying a routing result with fewer dead vias can increase the redundant via insertion rate, subsequently enhancing the yield of chips. This work presents, for the first time, a redundant-via-aware routing system to retain redundant via resources in track assignment, in which redundant vias are inserted in detailed routing. The proposed via prediction scheme performs trial route using L-shaped patterns to estimate via positions. Meanwhile, the proposed redundant-via-aware detailed router gradually relaxes the limitation on the number of generated dead vias during path searching to minimize the number of dead vias. Experimental results indicate that the proposed redundant-via-aware routing system is, to our knowledge, the first routing system that can achieve 100% redundant via insertion rate with all MCNC benchmark circuits. |