| Title | Statistical Timing Verification for Transparently Latched Circuits through Structural Graph Traversal |
| Author | *Xingliang Yuan, Jia Wang (Illinois Institute of Technology, U.S.A.) |
| Page | pp. 663 - 668 |
| Keyword | SSTA, latch, polynomial algorithm |
| Abstract | Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will adapt random delays at runtime due to time borrowing. The central problem to determine the timing yield is to compute the probability of the presence of a positive cycle in the latest latch timing graph. Existing algorithms are either optimistic since cycles are omitted or require iterations that cannot be polynomially bounded. In this paper, we present the first algorithm to compute such probability based on block-based statistical timing analysis that, first, covers all cycles through a structural graph traversal, and second, terminates within a polynomial number of statistical ``sum'' and ``max'' operations. Experimental results confirm that the proposed approach is effective and efficient. |
| Slides | |
| Title | A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine |
| Author | Jing Jia Nian, *Shih Heng Tsai, Chung Yang (Ric) Huang (GIEE, National Taiwan University, Taiwan) |
| Page | pp. 669 - 674 |
| Keyword | timing analysis, process variation, corner-based |
| Abstract | In this paper, we proposed a unified Multi-Corner Multi-Mode (MCMM) static timing analysis (STA) engine that can efficiently compute the worst-case delay of the process corners in various very large scaled circuits. Our key contributions include: (1) a seamless integration of the path- and parameter-based branch-and-bound algorithms so that the engine is very robust for different kinds of circuits, (2) an improved search space pruning technique, (3) a simple yet efficient critical path delay bound for the initial search space pruning. Our experimental results show that our engine can significantly outperform the prior MCMM STA approaches in various benchmark circuits with different number of process parameters. |
| Slides | |
| Title | Statistical Time Borrowing for Pulsed-Latch Circuit Designs |
| Author | *Seungwhun Paik, Lee-eun Yu, Youngsoo Shin (KAIST, Republic of Korea) |
| Page | pp. 675 - 680 |
| Keyword | pulsed-latch, time borrowing, statistical approach |
| Abstract | Pulsed-latch inherits the advantage of latch in less sequencing overhead while taking the advantage of flip-flop in its convenience during timing analysis. Even though this advantage comes from the fact that pulsed-latch uses a short pulse, it is still capable of a small amount of time borrowing. A problem of allocating pulse width (out of a few predefined widths), where each width is modeled by a random variable, is formulated for minimizing the clock period of pulsed-latch circuits; this is equivalent to assigning a random variable that represents the amount of time borrowed by the combinational block between each latch pairs. A statistical approach is important in this problem because assuming +3ó of all pulse widths does not represent the worst case. An allocation algorithm called SPWA as well as an algorithm to compute timing yield is proposed. In experiments with 45-nm technology, compared to the case of no time borrowing, the clock period was reduced by 12.2% and 11.7% on average when the yield constraint Yc is 0.85 and 0.95, respectively; this is compared to the deterministic counterpart called DPWA, which reduced the clock period by 7.6% and 7.3%. More importantly, DPWA failed to satisfy the yield constraints in four (out of eleven) circuits while the yield constraints were always satisfied in SPWA. |
| Title | Design Time Body Bias Selection for Parametric Yield Improvement |
| Author | *Cheng Zhuo, Yung-Hsu Chang, Dennis Sylvester, David Blaauw (Univ. of Michigan, Ann Arbor, U.S.A.) |
| Page | pp. 681 - 688 |
| Keyword | boay bias, power, delay, optimization, design time |
| Abstract | Circuits designed in aggressively scaled technologies face both stringent power constraints and increased process variability. Achieving high parametric yield is a key design objective, but is complicated by the correlation between power and performance. This paper proposes a novel design time body bias selection framework for parametric yield optimization while reducing testing costs. The framework considers both inter- and intra-die variations as well as power-performance correlations. This approach uses a feature extraction technique to explore the underlying similarity between the gates for effective clustering. Once the gates are clustered, a Gaussian quadrature based model is applied for fast yield analysis and optimization. This work also introduces an incremental method for statistical power computation to further reduce the optimization complexity. The proposed framework improves parametric yield from 39% to 80% on average for 11 benchmark circuits while runtime is linear with circuit size and on the order of minutes for designs with up to 15K gates. |