| Title | Minimizing Leakage Power in Aging-Bounded High-level Synthesis with Design Time Multi-Vth Assignment |
| Author | *Yibo Chen (Penn State University, U.S.A.), Yu Wang (Tsinghua University, China), Yuan Xie (Penn State University, U.S.A.), Andres Takach (Mentor Graphics Corporation, U.S.A.) |
| Page | pp. 689 - 694 |
| Keyword | high-level synthesis, aging, leakage power |
| Abstract | Aging effects (such as Negative Bias Temperature Instability
(NBTI)) can cause the temporal degradation of threshold voltage of
transistors, and have become major reliability concerns for
deep-sub-micron (DSM) designs. Meanwhile, leakage power
dissipation becomes dominant in total power as technology scales.
While multi-threshold voltage assignment has been shown as an
effective way to reduce leakage, the NBTI-degradation rates vary
with different initial threshold voltage assignment, and therefore
motivates the co-optimizations of leakage reduction and NBTI
mitigation. This paper minimizes leakage power during high-level
synthesis of circuits with bounded delay degradation (thus
guaranteed lifetime), using multi-Vth resource libraries. We
first propose a fast evaluation approach for NBTI-induced
degradation of architectural function units, and multi-Vth
resource libraries are built with degradation characterized for
each function unit. We then propose an aging-bounded high-level
synthesis framework, within which the degraded delays are used to
guide the synthesis, and leakage power is optimized through the
proposed aging-aware resource rebinding algorithm. Experimental
results show that, the proposed techniques can effectively reduce
the leakage power with an extra 26% leakage reduction, compared
to traditional aging-unaware multi-Vth assignment approach. |
| Title | A Global Interconnect Reduction Technique during High Level Synthesis |
| Author | Taemin Kim (Department of Computer Science, University of California, Los Angeles, U.S.A.), *Xun Liu (North Carolina State University, U.S.A.) |
| Page | pp. 695 - 700 |
| Keyword | High-level synthesis, Global Interconnect, Binding algorithm |
| Abstract | In this paper, we propose an interconnect binding algorithm during
high-level synthesis for global interconnect reduction. Our scheme is
based on the observation that not all functional units (FUs) operate
at all the time. When idle, FUs can be reconfigured as pass-through logic for data transfer, reducing interconnect requirement. Our algorithm formulates the interconnect reduction problem as a modified min-cost max-flow problem. It not only reduces the overall length of global interconnects but also minimizes the power overhead without introducing any timing violations. Experimental results show that, for a suite of digital processing benchmark circuits, our algorithm reduces global interconnects by 8.5% on the average in comparison to previously proposed schemes. It further lowers the overall design power by 4.8%. |
| Slides |
| Title | Incremental High-Level Synthesis |
| Author | Luciano Lavagno (Cadence Design Systems, U.S.A.), Mototsugu Fujii (Renesas Technology Corp., Japan), Alex Kondratyev (Cadence Design Systems, U.S.A.), Noriyasu Nakayama (Fujitsu Advanced Technologies, Japan), Mitsuru Tatesawa (Renesas Technology Corp., Japan), Yosinori Watanabe (Cadence Design Systems, U.S.A.), *Qiang Zhu (Cadence Design Systems, Japan) |
| Page | pp. 701 - 706 |
| Keyword | ECO, high-level synthesis, incremental synthesis |
| Abstract | The widespread acceptance of High-level synthesis
as a mainstream tool mostly depends on
its tight integration with the following RTL-to-GDSII design flow. A key
aspect is the handling of
so-called Engineering Change Orders (ECOs), i.e. minor changes required to fix small
functional bugs or meet performance requirements late in the design cycle.
Traditional high-level synthesis has attempted to optimize at best the output
logic. However, in the ECO scenario the goal is to
implement the required change with as few modifications as possible
to the RTL, logic netlist, placed netlist and layout.
In this paper
we show how, by judiciously changing the internal databases used by the tool to
match as much as possible the original design, one can achieve minimal impact
and implement ECOs in truly incremental mode, while full-blow re-synthesis would
lead to massive unnecessary downstream changes.
The tool essentially matches source constructs between the original and the ECO
design, and copies as many synthesis decisions as possible from the original
design to the ECO design. |
| Title | A High-Level Synthesis Flow for Custom Instruction Set Extensions for Application-Specific Processors |
| Author | Nagaraju Pothineni (Google, India, India), *Philip Brisk, Paolo Ienne (EPFL, Switzerland), Anshul Kumar, Kolin Paul (Indian Institute of Technology, Delhi, India) |
| Page | pp. 707 - 712 |
| Keyword | Synthesis, Instruction set extension |
| Abstract | Custom instruction set extensions (ISEs) are added to an extensible base processor to provide application-specific functionality at a low cost. As only one ISE executes at a time, resources can be shared. This paper presents a new high-level synthesis flow targeting ISEs. We emphasize new technique for resource allocation, binding, and port assignment during synthesis. Our method is derived from prior work on datapath merging, and increases area reduction by accounting for the cost of multiplexors that must be inserted into the resulting datapath to achieve multi-operational functionality. |
| Slides |