| Title | L-Shape Based Layout Fracturing for E-Beam Lithography |
| Author | Bei Yu, Jhih-Rong Gao, *David Z. Pan (University of Texas at Austin, U.S.A.) |
| Page | pp. 249 - 254 |
| Keyword | Electron Beam Lithography, Layout Fracturing, L-shape shot |
| Abstract | Layout fracturing is a fundamental step in mask data preparation and e-beam lithography (EBL) writing. To increase EBL throughput, recently a new L-shape writing strategy is proposed, which calls for new L-shape fracturing, versus the conventional rectangular fracturing. Meanwhile, during layout fracturing, one must minimize very small/narrow features, also called slivers, due to manufacturability concern. This paper addresses this new research problem of how to perform L-shaped fracturing with sliver minimization. We propose two novel algorithms. The first one, rectangular merging (RM), starts from a set of rectangular fractures and merges them optimally to form L-shape fracturing. The second algorithm, direct L-shape fracturing (DLF), directly and effectively fractures the input layouts into L-shapes with sliver minimization. The experimental results show that our algorithms are very effective. |
| Slides | |
| Title | High-throughput Electron Beam Direct Writing of VIA Layers by Character Projection using Character Sets Based on One-dimensional VIA Arrays with Area-efficient Stencil Design |
| Author | *Rimon Ikeno (The University of Tokyo, Japan), Takashi Maruyama (e-Shuttle, Inc., Japan), Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada (The University of Tokyo, Japan) |
| Page | pp. 255 - 260 |
| Keyword | Electron Beam Direct Writing, Character Projection, DFM, Layout Design, Interconnect Design |
| Abstract | For high-speed electron beam direct writing (EBDW) of VIA layers by Character projection (CP), number of VIAs in each CP shot should be increased, but it will result in huge number of CP characters for arbitrary VIA placements. We adopt one-dimensional VIA arrays as the basic character architecture to increase VIA numbers in a CP shot while saving the stencil area by superposed array characters. CP throughput is further improved by layout constraints for VIA arrangement. Our experimental results give estimated CP exposure counts less than 174G shot/wafer in 14nm technology. |
| Slides | |
| Title | Linear Time Algorithm to Find All Relocation Positions for EUV Defect Mitigation |
| Author | Yuelin Du (University of Illinois at Urbana-Champaign, U.S.A.), Hongbo Zhang, Qiang Ma (Synopsys, Inc., U.S.A.), *Martin D. F. Wong (University of Illinois at Urbana-Champaign, U.S.A.) |
| Page | pp. 261 - 266 |
| Keyword | EUV, Blank Defect Mitigation, Linear Time, Relocation Position, Multi-die Placement |
| Abstract | In EUV mask fabrication, die size is usually much smaller than the exposure field, such that one blank can accommodate multiple copies of a die. For thorough utilization of blank area, the number of valid dies that are not impacted by any defects should be maximized. To do so, all relocation positions to place a single valid die must be determined first. In this paper, we develop an efficient linear time algorithm to solve this problem. |
| Slides | |
| Title | Self-Aligned Double and Quadruple Patterning-Aware Grid Routing with Hotspots Control |
| Author | *Chikaaki Kodama (Toshiba Corporation, Japan), Hirotaka Ichikawa (Toshiba Microelectronics Corporation, Japan), Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto (Toshiba Corporation, Japan), Atsushi Takahashi (Tokyo Institute of Technology, Japan) |
| Page | pp. 267 - 272 |
| Keyword | Self-aligned double patterning, Self-aligned quadruple patterning, Grid routing, Lithography, Hotspot |
| Abstract | Self-Aligned Double and Quadruple Patterning (SADP, SAQP) have become the most promising processes for sub-20nm and sub-14nm node technology. We propose the simple grid routing method for SADP and SAQP possible to predict the wafer image. A new grid structure is prepared and mandrel patterns can be easily derived without complex coloring or decomposition. Also we try to reduce hotspots in a wafer image by dummy pattern flipping. Classical maze-routing algorithm is implemented and the effectiveness is confirmed. |
| Slides | |