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The 18th Asia and South Pacific Design Automation Conference

Session 3D  Hardware-Software Co-Optimization for Emerging NVMs
Time: 16:00 - 18:00 Wednesday, January 23, 2013
Chairs: Yun (Eric) Liang (Peking Univ., China), Yiran Chen (Univ. of Pittsburgh, U.S.A.)

3D-1 (Time: 16:00 - 16:30)
TitleCompiler-Assisted Refresh Minimization for Volatile STT-RAM Cache
AuthorQingan Li (City Univ. of Hong Kong, Hong Kong), Jianhua Li, Liang Shi (Univ. of Science and Tech. of China, China), *Chun Jason Xue (City Univ. of Hong Kong, Hong Kong), Yiran Chen (Univ. of Pittsburgh, U.S.A.), Yanxiang He (Wuhan Univ., China)
Pagepp. 273 - 278
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3D-2 (Time: 16:30 - 17:00)
TitleCurling-PCM: Application-Specific Wear Leveling for Phase Change Memory based Embedded Systems
Author*Duo Liu (Chongqing Univ., China), Tianzheng Wang (Univ. of Toronto, Canada), Yi Wang, Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Qingfeng Zhuge, Edwin Sha (Chongqing Univ., China)
Pagepp. 279 - 284
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3D-3 (Time: 17:00 - 17:30)
TitleSelectively Protecting Error-Correcting Code for Area-Efficient and Reliable STT-RAM Caches
Author*Junwhan Ahn (Seoul National Univ., Republic of Korea), Sungjoo Yoo (POSTECH, Republic of Korea), Kiyoung Choi (Seoul National Univ., Republic of Korea)
Pagepp. 285 - 290
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3D-4 (Time: 17:30 - 18:00)
TitleLoadsa: A Yield-Driven Top-Down Design Method for STT-RAM Array
AuthorWujie Wen, Yaojun Zhang, Lu Zhang, *Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Pagepp. 291 - 296
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