| Title | Optimization for Overdrive Signoff |
| Author | Tuck-Boon Chan, Andrew B. Kahng, *Jiajia Li, Siddhartha Nath (University of California, San Diego, U.S.A.) |
| Page | pp. 344 - 349 |
| Keyword | overdrive, signoff, overdesign, multi-mode, optimization |
| Abstract | In modern SOC implementations, multi-mode design is commonly used to achieve better circuit performance and power across voltage-scaling, “turbo” and other operating modes. Although there are many tools for multi-mode circuit implementation, to our knowledge there is no available systematic analysis or methodology for the selection of associated signoff modes. We observe that the selection of signoff modes has significant impact on circuit area, power and performance. For example, incorrect choice of signoff voltages for required overdrive frequencies can result in a netlist with 15% suboptimality in power or 21% in area. In this paper, we propose a concept of mode dominance which can be used as a guideline for signoff mode selection. Further, we also propose efficient circuit implementation flows to optimize the selection of signoff modes within several distinct use cases. Our results show that our proposed methodology provides 5-7% improvement in performance compared to the traditional “signoff and scale” method. The signoff modes determined by our methods result in only 0.6% overhead in performance and 8% overhead in power after implementation, compared to the optimal signoff modes. |
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| Title | Mountain-Mover: An Intuitive Logic Shifting Heuristic for Improving Timing Slack Violating Paths |
| Author | *Xing Wei, Wai-Chung Tang, Yu-Liang Wu (The Chinese University of Hong Kong, Hong Kong), Cliff Sze, Charles Alpert (IBM Austin Research Center, U.S.A.) |
| Page | pp. 350 - 355 |
| Keyword | logic rewiring, slack, timing optimization, post-placement |
| Abstract | Based on a simple intuitive notion, in this paper, we propose an efficient post-placement improvement scheme. Based on the given timing slack distribution of a circuit, a corresponding ``slack mountain map'' can be visualized with peaks and valleys representing the worst negative slack and non-critical positive slack areas respectively. Guided by this map, violating paths are improved while the slack mountain is flattened by applying a local logic perturbation technique (rewiring) repeatedly to shift logic resources from critical to non-critical areas. However, due to the locality property of the rewiring technique, to better avoid being stuck at local minimums, instead of firing rewiring operations from the peak top towards lower areas, we do this local logic shifting starting from ``sea areas'' (non-critical) towards peak (critical) areas. At the end, as the slack map is more flattened, a circuit with slack violations more evenly distributed can be yielded. Comparing to the recent work, our experimental results show that this scheme can obtain a better or comparable delay reduction but with CPU time one order of magnitude smaller. |
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| Title | Pulsed-Latch ASIC Synthesis in Industrial Design Flow |
| Author | *Sangmin Kim, Duckhwan Kim, Youngsoo Shin (Department of Electrical Engineering, KAIST, Republic of Korea) |
| Page | pp. 356 - 361 |
| Keyword | pulsed-latch, pulse generator, design flow, scan latch, ASIC |
| Abstract | Flip-flop has long been used as a sequencing element of choice in ASIC design; commercial synthesis tools have also been developed in this context. This work has been motivated by a question of whether existing CAD tools can be employed from RTL to layout while pulsed latch replaces flip-flop as a sequencing element. Two important problems have been identified and their solutions are proposed: placement of pulse generators and latches for integrity of pulse shape, and design of special scan latches and their selective use to reduce hold violations. A reference design flow has also been set up using published documents, in order to assess the proposed one. In 40-nm technology, the proposed flow achieves 20% reduction in circuit area and 30% reduction in power consumption, on average of 12 test circuits. |
| Title | Power Optimization for Application-Specific 3D Network-on-Chip with Multiple Supply Voltages |
| Author | *Kan Wang, Sheqin Dong (Tsinghua University, China) |
| Page | pp. 362 - 367 |
| Keyword | Layer Assignment, Multiple Supply Voltages, Application Specific 3D NoC, Inter-layer Communication, Power Consumption |
| Abstract | In this paper, a MSV-driven power optimization method is proposed for application-specific 3D NoC (MSV-3DNoC). A unified modeling method is presented for considering both layer assignment and voltage assignment, which achieves the best trade-off between core power and communication power. A 3D NoC synthesis is proposed to assign network components onto each layer and generate inter-layer interconnection. A global redistribution is applied to further reduce communication power. Experimental results show that compared to MSV-driven 2D NoC, the proposed method can improve total chip power greatly. |
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