| Title | Verifying Distributed Controllers using Time-Stamped ECAs |
| Author | *Matthias Kauer, Sebastian Steinhorst, Martin Lukasiewycz (TUM CREATE, Singapore), Dip Goswami, Reinhard Schneider, Samarjit Chakraborty (TU Munich, Germany) |
| Page | pp. 411 - 416 |
| Keyword | verification, event-count automata, linear control, timing analysis |
| Abstract | We study distributed controllers where sensor, controller, and actuator tasks are mapped onto different processors or Electronic Control Units (ECUs) in a distributed automotive architecture, communicating via a shared bus.
Controllers in such setups are designed with a sampling period equal to the worst-case sensor-to-actuator message delay. However, this assumption of all messages having to meet their deadlines is too pessimistic. The inherent robustness of most controllers allows some of the messages to miss their deadlines, while still meeting specified control performance constraints.
Given a controller, in this paper we first quantify the frequency of its acceptable deadline misses and represent this as a Linear Temporal Logic (LTL) formula.
Further, we model the distributed architecture as a network of time-stamped event count automata (TS-ECA). Such a network of TS-ECAs is then model-checked to verify whether it satisfies the LTL formula. The verification ensures that the controller may be mapped onto the architecture and the control performance constraints will be satisfied. We have implemented this methodology in the Symbolic Analysis Laboratory (SAL), which is a well-known framework
combining different tools for system verification. Our implementation and case studies using standard controller design shows the
applicability of our proposed controller/architecture co-verification.
It represents a significant improvement in current design flows where, although controller models are formally verified, their implementation on a distributed architecture is done in an ad hoc fashion with extensive testing and integration effort. |
| Title | Reliability Assessment of Safety-Relevant Automotive Systems in a Model-Based Design Flow |
| Author | *Sebastian Reiter, Michael Pressler, Alexander Viehl (FZI Forschungszentrum Informatik, Germany), Oliver Bringmann, Wolfgang Rosenstiel (University Tuebingen, Germany) |
| Page | pp. 417 - 422 |
| Keyword | reliability, model-based, error injection |
| Abstract | To support the reliability assessment of safety-relevant distributed automotive systems and reduce its complexity, this paper presents a novel approach that extends virtual prototyping towards error effect simulation. Besides the common functional and timed system simulation, error injection is used to stress error tolerance mechanisms. A quantitative assessment of the overall system reliability is performed by observing the system reactions and identifying incorrect system behavior. To foster the industrial application, the analysis is integrated in an model-based design flow, starting at the modeling level to assemble and parameterize the virtual prototype and to configure the analysis. The feasibility of the proposed approach is demonstrated by analyzing a representative safety-relevant automotive use case. |
| Slides |
| Title | Sequential Dependency and Reliability Analysis of Embedded System |
| Author | Hehua Zhang, *Yu Jiang (Tsinghua University, China), William N.N Hung (Synopsys, Inc., U.S.A.), Xiaoyu Song (Portland State University, U.S.A.), Jiaguang Sun (Tsinghua University, China) |
| Page | pp. 423 - 428 |
| Keyword | Dynamic Bayesian Network, embedded system, temporal correlations |
| Abstract | Embedded systems are becoming increasingly popular due to their widespread applications and the reliability of
them is a crucial issue. The complexity of the reliability analysis arises in handling the sequential feedback
that make the system output depends not only on the present input but also the internal state. In this paper,
we propose a novel
probabilistic model, named sequential dependency model (SDM), for the reliability analysis of embedded systems
with sequential feedback. It is constructed based on the structure of the system components and the signals among
them. We prove that the SDM model is s Dynamic Bayesian Network (DBN) that captures: the spatial dependencies between
system components in a single time slice, the temporal dependencies between system components of different time
slices, and the temporal dependencies due to the sequential feedback. We initiate the conditional probability
distribution (CPD) table of the SDM node with the failure probability of the corresponding system component. Then, the
SDM model handles the spatial-temporal correlations at internal components as well as the higher order temporal
correlations due to the sequential feedback with the computational mechanism of DBN, experiment results demonstrate
the accuracy of our model. |
| Slides |
| Title | Processor and DRAM Integration by TSV-Based 3-D Stacking for Power-Aware SOCs |
| Author | Shin-Shiun Chen, Chun-Kai Hsu, *Hsiu-Chuan Shih (National Tsing Hua University, Taiwan), Jen-Chieh Yeh (Industrial Technology Research Institute, Taiwan), Cheng-Wen Wu (National Tsing Hua University, Taiwan) |
| Page | pp. 429 - 434 |
| Keyword | 3D IC, DRAM, SOC, ESL, Power |
| Abstract | With the rapid popularization of mobile devices, the low-power and energy-efficient became far more important than the system operating frequency. This work demonstrates a processor and DRAM integration scheme by TSV-based 3-D stacking and the performance and energy efficiency is evaluated by an ESL design methodology. The integration scheme comprising Sans-Cache DRAM (SCDRAM) architecture which is designed under the power and energy considerations is explored. Experiment results show the proposed architecture can greatly reduce 80% energy while having 23.5% of system performance improvement. |
| Slides |