| Title | Optimizing Routability in Large-Scale Mixed-Size Placement |
| Author | Jason Cong (University of California, Los Angeles, U.S.A.), Guojie Luo (Peking University, China), *Kalliopi Tsota, Bingjun Xiao (University of California, Los Angeles, U.S.A.) |
| Page | pp. 441 - 446 |
| Keyword | placement, routing, congestion, routability |
| Abstract | One of the necessary requirements for the placement process is that it should be capable of generating routable solutions. This paper describes methods leading to the reduction of the routing congestion and the final routed wirelength
for large-scale mixed-size designs. In order to reduce routing congestion and improve routability, we propose blocking narrow regions on the chip. We also propose dummy-cell insertion inside regions characterized by reduced fixed-macro density. Our placer consists of three major components: (i) narrow channel reduction by performing neighbor-based fixed-macro inflation; (ii) dummy-cell insertion inside
large regions with reduced fixed-macro density; and (iii) preplacement inflation by detecting tangled logic structures in
the netlist and minimizing the maximum pin density. We
evaluated the quality of our placer using the newly released
DAC 2012 routability-driven placement contest designs and
we compared our results to the top four teams that participated in the placement contest. The experimental results
reveal that our placer improves the routability of the DAC
2012 placement contest designs and effectively reduces the
routing congestion. |
| Slides |
| Title | Symmetrical Buffered Clock-Tree Synthesis with Supply-Voltage Alignment |
| Author | Xin-Wei Shih (MediaTek, Taiwan), *Tzu-Hsuan Hsu (Linkwish, Taiwan), Hsu-Chieh Lee (Google, Taiwan), Yao-Wen Chang (National Taiwan University, Taiwan), Kai-Yuan Chao (Intel, U.S.A.) |
| Page | pp. 447 - 452 |
| Keyword | clock, skew, supply voltage, IR-drop, power |
| Abstract | For high-performance synchronous systems, nonuniform/non-ideal supply voltages of buffers (e.g., due to IR-drop) may incur a large clock skew and thus serious performance degradation. This paper addresses this problem and presents the first symmetrical buffered clock-tree synthesis flow that considers supply voltage differences of buffers. We employ a two-phase technique of bottom-up clock sink clustering to determine the tree topology, followed by top-down buffer placement and wire routing to complete the clock tree. At each level of processing, clock skew and wirelength are minimized by the determination of buffer embedding regions and the alignment of buffer supply voltages. Experimental results show that, on average, our method can achieve a 76% (respectively, 40%) clock skew reduction with marginal resource and runtime overheads, compared to the state-of-the-art work without supply voltage consideration (with an extension for supply voltages based on our top-down flow). With the skew reductions, our method can meet the stringent skew constraint set by the 2010 ISPD contest for all cases, while other counterparts cannot. In particular, our work provides a key insight into the importance of handling practical design issues (such as IR-drop) for real-world clock-tree synthesis. |
| Slides |