| Title | DARNS:A Randomized Multi-modulo RNS Architecture for Double-and-Add in ECC to Prevent Power Analysis Side Channel Attacks |
| Author | Jude Angelo Ambrose (University of New South Wales, Australia), *Hector Pettenghi, Leonel Sousa (Instituto de Engenharia de Sistemas e Computadores, Portugal) |
| Page | pp. 620 - 625 |
| Keyword | residue number systems, powe analysis side channel attacks, multi-modulo architectures |
| Abstract | Security in embedded systems is of critical importance since most of
our secure transactions are currently made via credit cards or mobile
phones. Power analysis based side channel attacks have been proved
as the most successful attacks on embedded systems to retrieve secret keys, allowing impersonation and theft. State-of-the-art solutions for such attacks in Elliptic Key Cryptography (ECC), mostly
in software, hinder performance and repeatedly attacked using improved techniques. To protect the ECC from both simple power
analysis and differential power analysis, as a hardware solution, we
propose to take advantage of the inherent parallelization capability
in Multi-modulo Residue Number Systems (RNS) architectures to
obfuscate the secure information. Random selection of moduli is
proposed to randomly choose the moduli sets for each key bit operation. This solution allows us to prevent power analysis, while still
providing all the benefits of RNS. In this paper, we show that the
DPA is indeed thwarted, as well as correlation analysis. |
| Slides |
| Title | ScanPUF: Robust Ultralow-Overhead PUF Using Scan Chain |
| Author | Yu Zheng, Aswin Raghav Krishna, *Swarup Bhunia (Case Western Reserve University, U.S.A.) |
| Page | pp. 626 - 631 |
| Keyword | PUF, DFT, Uniqueness, Stability, NBTI |
| Abstract | Physical Unclonable Functions (PUFs) have emerged as an attractive primitive to address diverse hardware security issues, such as chip authentication, intellectual property (IP) protection and cryptographic key generation. Existing PUFs, typically acquired and integrated in a design as a commodity, often incur considerable hardware overhead. Many of these PUFs also suffer from insufficient challenge-response pairs. In this paper, we propose {\em ScanPUF}, a novel PUF implementation using a common on-chip structure used for improving circuit testability, namely scan chain. It exploits path delay variations between the scan flip-flops in a scan chain to create high-quality (in terms of uniqueness and robustness) secret keys. Furthermore, since a scan chain provides large pool of scan paths to create a signature, we can achieve high volume of secret keys from each chip. Since it uses a prevalent on-chip structure, the overhead is extremely small (2.3% area of the RO-PUF), primarily contributed by small additional logic in the signature-generation cycle controller. Circuit-level simulation results with 1000 chips under inter- and intra-die process variations show high uniqueness of 49.9% average inter-die Hamming distance and good reproducibility of 5% intra-die Hamming distance below 85 $^\circ$C. The temporal variations due to device aging effect e.g. bias temperature instability (BTI) lead to only 4% unstable bits for ten-year usage. The experimental evaluation on FPGA (Altera Cyclone-III) exhibits 47.1% average inter-Hamming distance, as well as 3.2% unstable bits at room temperature. |
| Slides |
| Title | An Efficient Compression Scheme for Checkpointing of FPGA-Based Digital Mockups |
| Author | *Ting-Shuo Chou (University of California, Irvine, U.S.A.), Chen Huang, Bailey Miller (University of California, Riverside, U.S.A.), Tony Givargis (University of California, Irvine, U.S.A.), Frank Vahid (University of California, Riverside, U.S.A.) |
| Page | pp. 632 - 637 |
| Keyword | Digital Mockups, Test Automation, Cyber-Physical Systems, Medical Cyber-Physical Systems, Hardware-in-the-Loop |
| Abstract | This paper outlines a transparent and nonintrusive checkpointing mechanism for use with FPGA-based digital mockups. A digital mockup is an executable model of a physical system, implemented on an FPGA, and used for real-time test and validation of cyber-physical devices that interact with the physical system. These digital mockups are typically defined in terms of a large set of ordinary differential equations (ODEs). A checkpoint is a snapshot of the internal state of the model at a specific point in time as captured by some controller that resides on the same FPGA. A further requirement is that the model continues uninterrupted execution during a checkpointing operation. Once a checkpoint is created, the corresponding state information is transferred from the FPGA to a host computer for visualization and other off-chip processing. We outline the architecture of a checkpointing controller that captures and transfers the state information at a desired clock cycle using an aggressive compression technique. Our controller achieves 90% reduction in the amounts of data that is transferred from the FPGA to the host computer under periodic checkpointing scenarios. |
| Slides |
| Title | Maximizing Return on Investment of a Grid-Connected Hybrid Electrical Energy Storage System |
| Author | Di Zhu, Yanzhi Wang, Siyu Yue, *Qing Xie (University of Southern California, U.S.A.), Naehyuck Chang (Seoul National University, Republic of Korea), Massoud Pedram (University of Southern California, U.S.A.) |
| Page | pp. 638 - 643 |
| Keyword | return on investment, capital cost, hybrid electrical energy storage system |
| Abstract | This paper is the first to present a comprehensive analysis of the profitability of the hybrid electrical energy storage (HEES) systems while further providing a HEES design and control optimization framework to maximize the total return on investment (ROI). The solution consists of two steps: (i) Derivation of an optimal HEES management policy to maximize the daily energy cost saving and (ii) Optimal design of the HEES system to maximize the amortized annual profit under budget and system volume constraints. We consider a HEES system comprised of lead-acid and Li-ion batteries for a case study. The optimal HEES system achieves an annual ROI of up to 60% higher than a lead-acid battery-only system (Li-ion battery-only) system. |
| Slides |