| Title | A Topology-Based ECO Routing Methodology for Mask Cost Minimization |
| Author | *Po-Hsun Wu, Shang-Ya Bai, Tsung-Yi Ho (National Cheng Kung University, Taiwan) |
| Page | pp. 507 - 512 |
| Keyword | ECO, Routing, Mask Cost |
| Abstract | Engineering Change Order (ECO) routing, which is a complicated and difficult task due to limited routing resource and increasing design rules, is requested in later design stage for the purpose of delay and noise optimization. After ECO routing procedure, some routing layers may be modified and the corresponding masks are needed to be remanufactured which leads to high mask re-spin cost. Although several ECO routers had been proposed to obtain a routing solution based on different design objectives, mask re-spin cost still cannot be effectively reduced because the ECO routing problem is handled in a sequential manner. This paper presents a three-stage ECO routing flow which can simultaneously route all ECO nets while considering routing layer minimization. Initially, several routing paths for each ECO net are efficiently generated and an Integer Linear Programming (ILP) model is developed to simultaneously determine the routing path of each ECO net to minimize the number of changed masks. Moreover, a minimum-cost-maximum-flow (MCMF) algorithm is applied to further reduce the number of changed masks. Experimental results demonstrate that our proposed ECO routing flow can effectively reduce the number of changed masks with only negligible wirelength and via overhead. |
| Title | BOB-Router: A New Buffering-Aware Global Router with Over-the-Block Routing Resources Optimization |
| Author | Yilin Zhang (University of Texas at Austin, U.S.A.), Salim Chowdhury (Oracle, U.S.A.), *David Z. Pan (University of Texas at Austin, U.S.A.) |
| Page | pp. 513 - 518 |
| Keyword | Routing, Over-the-block, Congestion, Slew |
| Abstract | In this paper, we propose a new global router, BOB-Router, endowed with the ability to use over-the-block routing resources to the greatest extent in additional to traditional routing concepts of minimizing wirelength, via count and overflow. In previous global routing formulations, the routing resources over the IP blocks were either dealt as routing blockages leading to a significant waste, or simply treated in the same way as outside-the-block routing resources, which would violate the slew constraints and thus fail buffering. Utilizing over-the-block routing resources could dramatically improve the routing solution, yet requires special attention, since the slew, affected by different RC on different metal layers, must be constrained by buffering and is easily violated. Moreover, even of all nets are slew-legalized, the routing solution could still suffer from heavy congestion problem. For the first time, BOB-Router tries to solve the over-the-block global routing problem through minimizing overflows, wirelength and via count simultaneously without violating slew constraints. BOB-Router generates a slew-legalized initial solution followed by an Lagragian-multiplier-based pricing phase and RC-constrained A* search to help explore new buffering-aware topologies on all metal layers. Our experimental results show that BOB-Router completely satisfies the slew constraints and significantly outperforms the obstacle-avoiding global routers in terms of wirelength, via count and overflows. |
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| Title | Routability-Driven Bump Assignment for Chip-Package Co-Design |
| Author | Meng-Ling Chen, Tu-Hsiung Tsai, *Hung-Ming Chen (National Chiao Tung University, Taiwan), Shi-Hao Chen (Global Unichip Corporation, Taiwan) |
| Page | pp. 519 - 524 |
| Keyword | Bump assignment, co-design |
| Abstract | In current chip and package designs, it is a bottleneck to simultaneously optimize both pin assignment and pin routing for different design domains (chip, package, and board). Usually, the whole process costs a huge manual effort and multiple iterations thus reducing profit margin. Therefore, we propose a fast heuristic chip-package co-design algorithm in order to automatically obtain a bump assignment which introduces high routability both in RDL routing and package routing (100\% in our real case). Experimental results show that the proposed method (inspired by board escape routing algorithms) automatically finishes bump assignment, RDL routing and package routing in a short time, while the traditional co-design flow requires weeks even months. |
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| Title | VFGR: A Very Fast Parallel Global Router with Accurate Congestion Modeling |
| Author | *Zhongdong Qi, Yici Cai, Qiang Zhou (Tsinghua University, China), Zhuoyuan Li, Mike Chen (Nimbus Automation Technologies, China) |
| Page | pp. 525 - 530 |
| Keyword | Global Routing, Parallelization, Congestion Modeling |
| Abstract | With the rapid growth of design size and complexity, global routing has always been a hard problem. Several new factors contribute to global routing congestion and can only be measured and optimized in 3-D global routing rather than 2-D routing. To more accurately reflect modern design rule requirements and various new factors, we propose a practical congestion model in global routing. To achieve better global and detailed routing solution quality, we propose a 3-D global router VFGR with parallel computing using proposed congestion model. Experimental results show that VFGR can achieve comparable or better solution quality with two start-of-the-art global routers with shorter runtime. It is also demonstrated that adopting proposed congestion model in global routing, higher solution quality and much shorter runtime can be achieved in detailed routing stage. |
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