| Title | PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices |
| Author | *Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta (University of California, Los Angeles, U.S.A.) |
| Page | pp. 818 - 824 |
| Keyword | Tunneling(T) FET, silicon-on-insulator (SOI), circuit-level device evaluation, Pareto optimization, simulation based optimization |
| Abstract | Evaluation of novel devices in a circuit context is crucial to identifying and maximizing their value. We propose a new framework, PROCEED, and metrics for accurate device-circuit co-evaluation by properly optimizing digital circuit benchmarks. PROCEED assesses technology suitability over a wide operating region (MHz to GHz) by leveraging available circuit knobs (Vt assignment, power management, sizing, etc.) and is up to 21X more accurate than existing methods. As an example, we use PROCEED to compare CMOS and tunneling transistor devices. |
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| Title | Modeling and Design Analysis of 3D Vertical Resistive Memory - A Low Cost Cross-Point Architecture |
| Author | *Cong Xu, Dimin Niu (Pennsylvania State University, U.S.A.), Shimeng Yu (Arizona State University, U.S.A.), Yuan Xie (Advanced Micro Devices, China/Pennsylvania State University, U.S.A.) |
| Page | pp. 825 - 830 |
| Keyword | ReRAM, 3D |
| Abstract | Resistive Random Access Memory (ReRAM) is one of the most promising emerging non-volatile memory (NVM) candidates due to its fast read/write speed, excellent scalability and low-power operation. Recently proposed 3D vertical cross-point ReRAM (3D-VRAM) architecture attracts a lot of attention because it offers a cost-competitive solution for NAND Flash replacement. In this work, we first develop an array-level model which includes the geometries and properties of all the components in the 3D structure. The model is capable of analyzing the read/write noise margin of a 3D-VRAM array in the presence of the sneak leakage current and voltage drop. Then we build a system-level design tool that is able to explore the design space with specified constraints and find the optimal design points with different targets. We also study the impact of different design parameters on the array size, bit density and overall cost-per-bit. Compared to the state-of-the-art 3D horizontal ReRAM (3D-HRAM), the 3D-VRAM shows great cost advantage when stacking more than 16 layers. |
| Title | The Stochastic Modeling of TiO2 Memristor and Its Usage in Neuromorphic System Design |
| Author | Miao Hu (University of Pittsburgh, U.S.A.), Yu Wang (Tsinghua University, China), Qinru Qiu (Syracuse University, U.S.A.), Yiran Chen, *Hai Li (University of Pittsburgh, U.S.A.) |
| Page | pp. 831 - 836 |
| Keyword | Memristor, Stochastic model, Neuromorphic system |
| Abstract | Memristor–the fourth basic circuit element, has shown great potential in neuromorphic circuit design for its unique synapse-like feature. However, there still exists a large gap between the theoretical memristor characteristics and the experimental data obtained from real device measurements. For instance, though the continuous resistance state of memristor has been expected to facilitate neuromorphic circuit designs, obtaining and maintaining an arbitrary intermediate state cannot be well controlled in nowadays memristive system. Moreover, the stochastic behaviors have been widely observed in real device measurement. To facilitate the investigation on memristor-based hardware implementation, we first built a stochastic behavior model for TiO2 memristive devices based on the real experimental results. We then proposed a macro cell design composed of multiple parallel connecting memristors. By leveraging the stochastic behavior of memristors, the macro cell can be successfully used as the weight storage unit and stochastic neuron – the two fundamental components widely adopted in neural networks, providing a feasible solution in memristor-based hardware implementation of neuromorphic systems. |
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| Title | Through-Silicon-Via Inductor: Is It Real or Just A Fantasy? |
| Author | *Umamaheswara Rao Tida (Missouri University of Science and Technology, U.S.A.), Cheng Zhuo (Intel Research, U.S.A.), Yiyu Shi (Missouri University of Science and Technology, U.S.A.) |
| Page | pp. 837 - 842 |
| Keyword | 3D IC, TSV Inductor, Through-Silicon-Vias, Micro-channel, On-chip inductors |
| Abstract | Through-silicon-vias (TSVs) can potentially be used to implement inductors in three-dimensional (3D) integrated systems for minimal footprint and large inductance. However, different from conventional 2D spiral inductors, TSV inductors are fully buried in the lossy substrate, thus suffering from inferior quality factors. As such, literature has pointed out that TSV inductors should be used when area is the only concern, which essentially means they are useless. In this paper, we propose a novel shield mechanism utilizing the micro-channel, a technique conventionally used for heat removal, to reduce the substrate loss. The technique increases the quality factor and the inductance of the TSV inductor by up to 21x and 17x respectively. It enables us to implement TSV inductors of up to 38x smaller area and 33% higher quality factor, compared with spiral inductors of the same inductance. To the best of the authors’ knowledge, this is the first proposal on improving quality factor of TSV inductors. We hope our study shall point out a new and exciting research direction for 3D IC designers. |
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