| Title | Design and Control Methodology for Fine Grain Power Gating Based on Energy Characterization and Code Profiling of Microprocessors |
| Author | *Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Institute of Technology, Japan), Weihan Wang, Hideharu Amano (Keio University, Japan), Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki (Tokyo University of Agriculture and Technology, Japan), Masaaki Kondo (The University of Electro-Communications, Japan), Hiroshi Nakamura (University of Tokyo, Japan) |
| Page | pp. 843 - 848 |
| Keyword | power gating |
| Abstract | This paper describes design and control scheme of an embedded processor whose internal function units are power gated at instruction-by-instruction basis. Enabling/disabling the power gating is adaptively controlled under the support of on-chip leakage monitors and the operating system to minimize energy overhead due to sleep-in and wakeup. Measured results of the fabricated chip demonstrated that our approach reduces energy by up to 15% for the range of 25-85C as compared to the conventional fine-grain power gating technique. |
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| Title | A Hybrid Random Walk Algorithm for 3-D Thermal Analysis of Integrated Circuits |
| Author | *Yuan Liang, Wenjian Yu (Tsinghua University, China), Haifeng Qian (IBM T. J. Watson Research Center, U.S.A.) |
| Page | pp. 849 - 854 |
| Keyword | thermal analysis, random walk method |
| Abstract | In this work, a hybrid random walk method is proposed for the thermal analysis of integrated circuits. Preserving the advantage of generic random walk method (GRW), i.e. the suitability for simulating local hot-spots, the proposed techniques largely reduce its runtime for accurate high-resolution simulation, and is suitable for the realistic pyramid-shape IC model. This is achieved by combining the GRW and the floating random walk techniques, and a novel usage of rectangular cuboid transition domain. The techniques to handle the Neumann boundary and convective boundary in thermal simulation are also discussed. Numerical experiments on several IC test cases validate the efficiency and accuracy of the proposed techniques, and demonstrate more than 100X speedup over the GRW method. |
| Title | LightSim : A Leakage Aware Ultrafast Temperature Simulator |
| Author | Smruti R. Sarangi, *Gayathri Ananthanarayanan, M. Balakrishnan (IIT Delhi, India) |
| Page | pp. 855 - 860 |
| Keyword | temperature, estimation, thermal, analysis |
| Abstract | In this paper, we propose the design of an ultra-fast temperature simulator, LightSim, which can perform both steady state and transient thermal analysis, and also take the effect of leakage power into account. We use a novel Hankel transform based technique to derive a transient version of the Green's function for a chip, which takes into account the feedback loop between temperature and leakage. Subsequently, we calculate the temperature map of a chip by convolving the derived Green's function with the power map. Our simulator is at least 3500 times faster than HotSpot, and at least 2.3 times faster than competing research prototypes. The total error is limited to 0.18K. |
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| Title | Fast Vectorless Power Grid Verification Using Maximum Voltage Drop Location Estimation |
| Author | Wei Zhao, Yici Cai, *Jianlei Yang (Tsinghua University, China) |
| Page | pp. 861 - 866 |
| Keyword | Power Grid, Vectorless Verification, Voltage Drop, Location Estimation |
| Abstract | Power grid integrity verification is critical for reliable chip design. Vectorless power grid verification provides a promising approach to evaluate the worst-case voltage fluctuations without the detailed information of circuit activities. Vectorless verification is usually required to solve numerous linear programming problems to obtain the worst-case voltage fluctuation throughout the grid, which is extremely time-consuming for large-scale verification. In this paper, a maximum voltage drop location estimation approach is proposed for efficient vectorless verification. The power grid nodes are grouped into disjoint subsets, and an estimation strategy is utilized to roughly locate the nodes which have the worst-case voltage drop in each group. Consequently, the verification problem size can be significantly reduced compared with accurate verification. Experimental results show that the proposed approach can achieve remarkable speedups with acceptable accuracy loss. |
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