| Title | (Invited Paper) Advanced Multi-Patterning and Hybrid Lithography Techniques |
| Author | *Fedor G. Pikus, Andres Torres (Mentor Graphics, U.S.A.) |
| Page | pp. 611 - 616 |
| Keyword | DFM, MP, DSA, semiconductor, manufacturing |
| Abstract | We present an overview of several techniques that are used when the layout pitch and feature size become significantly smaller than the minimum resolution of the lithographic process. We consider several multi-patterning (MP) techniques, in which a single layer is decomposed into two or more masks and printed in multiple stages. We also introduce the direct self-assembly (DSA) technology, where features several times smaller than the minimum lithographic resolution form spontaneously due to self-assembling, or self-organizing, formation of block copolymers. |
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| Title | (Invited Paper) Recent Research Development and New Challenges in Analog Layout Synthesis |
| Author | *Mark Po-Hung Lin (National Chung Cheng University, Taiwan), Yao-Wen Chang (National Taiwan University, Taiwan), Chih-Ming Hung (MediaTek, Taiwan) |
| Page | pp. 617 - 622 |
| Keyword | Analog layout, placement, routing, migration, knowledge mining |
| Abstract | Analog and mixed-signal integrated circuits play an important role in many modern emerging system-on-chip (SoC) design applications. With the expansion of the markets of those applications, the demands of analog/mixed-signal ICs have been dramatically increased. Although analog/mixed-signal ICs have gained more and more importance and demands in modern SoC applications, the development of analog electronic design automation (EDA) tools is still farther behind that of digital EDA tools. As a result, analog/mixed-signal IC design, especially the analog layout design, is still a manual, time-consuming, and error-prone task. In order to speedup modern SoC design for large varieties of emerging applications, it is required to develop novel analog/mixed-signal IC deign methodologies and algorithms, as well as new analog EDA tools. The purpose of this paper is to summarize recent research progress during the past decade, address new analog layout design challenges in advanced technology nodes, and facilitate more research activities in analog layout synthesis. |
| Title | (Invited Paper) To Detect, Locate, and Mask Hardware Trojans in Digital Circuits by Reverse Engineering and Functional ECO |
| Author | *Xing Wei, Yi Diao, Yu-Liang Wu (Easy-Logic Technology Ltd., Hong Kong) |
| Page | pp. 623 - 630 |
| Keyword | Hardware Trojan, Formal verification, Reverse Engineer, Functional ECO, Logic Rewiring |
| Abstract | During the design phase, a specification may be tampered directly by dishonest engineers (or industry spy), or may be tampered indirectly through the use of malicious modules from a third party Intellectual Property (3PIP) block vendors. During integration and fabrication, the chips may also be tampered by the untrusted system integrator. Particularly for high-end commercial or classified military chips, Hardware Trojan (HT) Detect-Locate-and-Mask (DL&M) is crucially necessary so as to make sure a design is produced exactly as the original specification. Our objectives are (1) to detect any functionality difference which might be caused by bugs or HTs, (2) to locate/output the difference circuitry to correct the bugs or to investigate the tampering intention or purpose, and (3) to kill (mask) the HTs by restoring the chip’s functionality back to golden with a minimum circuitry change. Besides blocking the plotted damage in an early stage and pointing the spy source by revealing the HT intention, the masking circuit revision must also be minimized to avoid affecting the chip performance (timing) too much. In this paper, we propose a scheme that integrates reverse engineering, formal verification, functional ECO, and logic rewiring to detect, locate and mask Hardware Trojans with minimized cost. This formal verification based scheme can guarantee catching 100% of the hidden combinational circuit HTs and can handle multiple HTs (no number limit) automatically in one run. Some techniques within our scheme won the first places of the CAD Contests at ICCAD 2012, 2013, and 2014 |
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