Best Paper

ASP-DAC 2024 4C-1

FineMap: A Fine-grained GPU-parallel LUT Mapping Engine

FineMap: A Fine-grained GPU-parallel LUT Mapping Engine
Chinese University of Hong Kong, Hong Kong
Tianji Liu
Huawei Noah's Ark Lab, Hong Kong SAR, Hong Kong
Lei Chen
Huawei Noah's Ark Lab, Hong Kong SAR, Hong Kong
Xing Li
Huawei Noah's Ark Lab, Hong Kong SAR, Hong Kong
Mingxuan Yuan
Chinese Univ. of Hong Kong, Hong Kong
Evangeline F.Y. Young

ASP-DAC 2024 6D-1

SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation

SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation
Zhejiang University, China
Xiao Dong
Zhejiang University, China
Songyu Sun
Zhejiang University, China
Yangfan Jiang
University of Pittsburgh, USA
Jingtong Hu
Zhejiang Univ./Zhejiang ICsprout Semiconductor, China
Dawei Gao
Zhejiang Univ./Key Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province, China
Cheng Zhuo

ASP-DAC 2023 2C-2

Approximate Floating-Point FFT Design with Wide Precision-Range and High Energy Efficiency

Approximate Floating-Point FFT Design with Wide Precision-Range and High Energy Efficiency
Zhejiang University, China
Chenyi Wen
Zhejiang University, China
Ying Wu
Zhejiang University, China
Xunzhao Yin
Zhejiang University, China
Cheng Zhuo

ASP-DAC 2023 3D-1

Rethink before Releasing Your Model: ML Model Extraction Attack in EDA

Rethink before Releasing your Model: ML Model Extraction Attack in EDA
Duke University, U.S.A
Chen-Chia Chang
Duke University, U.S.A
Jingyu Pan
Hong Kong University of Science and Technology, Hong Kong
Zhiyao Xie
Texas A&M University, U.S.A
Jiang Hu
Duke University, U.S.A
Yiran Chen

ASP-DAC 2022 3D-1

Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems

Zerun LiXiaoming ChenYinhe Han
Chinese Academy of Sciences, China
Zerun Li, Xiaoming Chen, Yinhe Han

ASP-DAC 2022 4B-1

Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization

chung-kuan chengchia-tung hochester holtz
University of California, San Diego, USA
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz

ASP-DAC 2021 2B-1

Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars

Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars
Tech. Univ. of Munich, Germany
Shuhang Zhang
Duke Univ., USA
Hai Li
Tech. Univ. of Munich,Germany
Ulf Schlichtmann

ASP-DAC 2021 2E-1

TreeNet: Deep Point Cloud Embedding for Routing Tree Construction

TreeNet: Deep Point Cloud Embedding for Routing Tree Construction
Chinese Univ. of Hong Kong, Hong Kong
Wei Li
Chinese Univ. of Hong Kong, Hong Kong
Yuxiao Qu
Giga Design Automation, China
Gengjie Chen
Chinese Univ. of Hong Kong, Hong Kong
YuzheMa
Chinese Univ. of Hong Kong, Hong Kong
Bei Yu

ASP-DAC 2020 7B-3

Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture

Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture
Univ. of Texas, Austin, USA
Jiaqi Gu
Univ. of Texas, Austin, USA
Zheng Zhao
Univ. of Texas, Austin, USA
Chenghao Feng
Univ. of Texas, Austin, USA
Mingjie Liu
Univ. of Texas, Austin, USA
Ray T. Chen
Univ. of Texas, Austin, USA
David Z. Pan

ASP-DAC 2020 2D-1

Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability

Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability
Sheng-Jung Yu
National Taiwan Univ., Taiwan
Chen-Chien Kao
National Taiwan Univ., Taiwan
Chia-Han Huang
National Taiwan Univ., Taiwan
Iris Hui-Ru Jiang
National Taiwan Univ., Taiwan

ASP-DAC 2019 2B-1

GraphSAR: A Sparsity-Aware Processing-in-Memory Architecture for Large-Scale Graph Processing on ReRAMs

GraphSAR: A Sparsity-Aware Processing-in-Memory Architecture for Large-Scale Graph Processing on ReRAMs
Tsinghua Univ., China
Guohao Dai
Massachusetts Inst. of Tech., U.S.A.
Tianhao Huang
Tsinghua Univ., China
Yu Wang
Tsinghua Univ., China
Huazhong Yang
Univ. of California, Berkeley, U.S.A.
John Wawrzynek

ASP-DAC 2019 3D-1

Energy-Efficient, Low-Latency Realization of Neural Networks through Boolean Logic Minimization

Energy-Efficient, Low-Latency Realization of Neural Networks through Boolean Logic Minimization
USC, U.S.A.
Mahdi Nazemi, Ghasem Pasandi, Massoud Pedram

ASP-DAC 2018 3B-4

Process Variation Aware Data Management for Magnetic Skyrmions Racetrack Memory

Process Variation Aware Data Management for Magnetic Skyrmions Racetrack Memory
Duke Univ, U.S.A.
Fan Chen
Univ of Pittsburgh, U.S.A.
Zheng Li
Beihang Univ, China
Wang Kang, Weisheng Zhao
Duke Univ, U.S.A.
Hai Li, Yiran Chen

ASP-DAC 2017 9C-1

Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses

Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses
Univ. of Pittsburgh, U.S.A.
Yandan Wang, Wei Wen, Linghao Song, Hai Li

ASP-DAC 2017 8B-1

Spendthrift: Machine Learning Based Resource and Frequency Scaling for Ambient Energy Harvesting Nonvolatile Processors

Spendthrift: Machine Learning Based Resource and Frequency Scaling for Ambient Energy Harvesting Nonvolatile Processors
Penn State Univ., U.S.A.
Kaisheng Ma, Xueqing Li, Srivatsa Rangachar Srinivasa, John (Jack) Sampson, Vijaykrishnan Narayanan
Tsinghua Univ., China
Yongpan Liu
UCSB, U.S.A.
Yuan Xie

ASP-DAC 2016 5C-1

Lattice-Based Boolean Diagrams: Canonical, Order-Independent Graphical Representations of Boolean Functions

Lattice-Based Boolean Diagrams: Canonical, Order-Independent Graphical Representations of Boolean Functions
Univ. of California, Irvine
Ahmed Nassar, Fadi Kurdahi

ASP-DAC 2016 7B-1

Netlist Reverse Engineering for High-Level Functionality Reconstruction

Netlist Reverse Engineering for High-Level Functionality Reconstruction
Univ. of Central Florida
Travis Meade, Shaojie Zhang, Yier Jin

ASP-DAC 2015 1C-1

Quantitative Modeling of Racetrack Memory, A Tradeoff among Area, Performance, and Power

Quantitative Modeling of Racetrack Memory, A Tradeoff among Area, Performance, and Power
CECA, Peking University, China
Chao Zhang, Guangyu Sun, Weiqi Zhang
University of Pittsburgh, U.S.A.
Fan Mi, Hai Li
Spintronics Interdisciplinary Center, Beihang University, China
Weisheng Zhao

ASP-DAC 2014 2B-1

Flexible Packed Stencil Design with Multiple Shaping Apertures for E-Beam Lithography

Flexible Packed Stencil Design with Multiple Shaping Apertures for E-Beam Lithography
Iowa State Univ., U.S.A.
Chris Chu
National Tsing Hua Univ., Taiwan
Wai-Kei Mak

ASP-DAC 2013 1B-1

A Case for Wireless 3D NoCs for CMPs

A Case for Wireless 3D NoCs for CMPs
Keio Univ., Japan
Hiroki Matsutani
Carnegie Mellon Univ., U.S.A.
Paul Bogdan, Radu Marculescu
Keio Univ., Japan
Yasuhiro Take, Daisuke Sasaki, Hao Zhang
NII, Japan
Michihiro Koibuchi
Keio Univ., Japan
Tadahiro Kuroda, Hideharu Amano

ASP-DAC 2013 2C-1

I-LUTSim: An Iterative Look-Up Table Based Thermal Simulator for 3-D Ics

I-LUTSim: An Iterative Look-Up Table Based Thermal Simulator for 3-D Ics
National Chiao Tung Univ., Taiwan
Chi-Wen Pan, Yu-Min Lee
ITRI, Taiwan
Pei-YuHuang
National Chiao Tung Univ., Taiwan
Chi-Ping Yang
ITRI, Taiwan
Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai

ASP-DAC 2012 2C-1

An Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology

National Chiao Tung University, Taiwan
Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen
Freescale Semiconductor Inc., U.S.A.
Jayanta Bhadra

ASP-DAC 2012 3C-1

EPIC: Efficient Prediction of IC Manufacturing Hotspots With A Unified Meta-Classification Formulation

The University of Texas at Austin, U.S.A.
Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan

ASP-DAC 2011 3A-1

Co-Design of Cyber-Physical Systems via Controllers with Flexible Delay Constraints

Co-Design of Cyber-Physical Systems via Controllers with Flexible Delay Constraints
Tech. Univ. of Munich, Germany
Dip Goswami, Reinhard Schneider, Samarjit Chakraborty

ASP-DAC 2010 2C-2 

SCGPSim: A Fast SystemC Simulator on GPUs

SCGPSim: A Fast SystemC Simulator on GPUs
Virginia Polytechnic Inst. and State Univ., U.S.A.
Mahesh Nanjundappa
Univ. of Waterloo, Canada
Hiren D Patel
Virginia Polytechnic Inst. and State Univ., U.S.A.
Bijoy A Jose, *Sandeep K Shukla

ASP-DAC 2010 8A-1 

A New Graph-theoretic, Multi-objective Layout Decomposition Framework for Double Patterning Lithography

A New Graph-theoretic, Multi-objective Layout Decomposition Framework for Double Patterning Lithography
Univ. of Texas, Austin, U.S.A.
Jae-Seok Yang
Intel, U.S.A.
Katrina Lu
IBM Research, U.S.A.
MinSik Cho
Univ. of Texas, Austin, U.S.A.
Kun Yuan, David Z. Pan

ASP-DAC 2009 1C-1 

FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization

FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization
Univ. of Illinois, Urbana-Champaign, United States
Gregory Lucas, Scott Cromar, Deming Chen

ASP-DAC 2009 5C-1

Efficiently Finding the 'Best' Solution with Multi-Objectives from Multiple Topologies in Topology Library of Analog Circuit

Efficiently Finding the 'Best' Solution with Multi-Objectives from Multiple Topologies in Topology Library of Analog Circuit
Fujitsu Laboratories Ltd., Japan
Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya

ASP-DAC 2008 1A-1

Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning

Pennsylvania State Univ., United States
Feng Wang, Xiaoxia Wu, Yuan Xie

ASP-DAC 2008 9A-1

An Efficient, Fully Nonlinear, Variability-Aware Non-Monte-Carlo Yield Estimation Procedure with Applications to SRAM Cells and Ring Oscillators

Univ. of Minnesota, United States
Chenjie Gu, Jaijeet Roychowdhury

ASP-DAC 2007 3B-2

Protocol Transducer Synthesis using Divide and Conquer Approach

Protocol Transducer Synthesis using Divide and Conquer Approach
Univ. of Tokyo, Japan
Shota Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita

ASP-DAC 2007 5A-1 

A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects

A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects
Texas A&M Univ., United States
Ying Zhou
Pextra Corp., United States
Zhuo Li
Texas A&M Univ., United States
Yuxin Tian, *Weiping Shi
IBM, United States
Frank Liu

ASP-DAC 2006 1B-1

Constraint-Driven Bus Matrix Synthesis for MPSoC

Constraint-Driven Bus Matrix Synthesis for MPSoC
Univ. of California, Irvine, United States
Sudeep Pasricha, Nikil Dutt
Conexant, United States
Mohamed Ben-Romdhane

ASP-DAC 2006 3C-1

Post-Routing Redundant Via Insertion for Yield/Reliability Improvement

Post-Routing Redundant Via Insertion for Yield/Reliability Improvement
National Tsing Hua Univ., Taiwan
Kuang-Yao Lee, Ting-Chi Wang

ASP-DAC 2004 8B-1

Representative Frequency for Interconnect R(f)L(f)C Extraction

Kyoto Univ., Japan
A. Tsuchiya, M. Hashimoto, H. Onodera

ASP-DAC 2004 6D-1

Preserving Synchronizing Sequences of Sequential Circuits After Retiming

Univ. of Michigan, USA
M. Mneimneh, K. Sakallah
Intel Corp., USA
J. Moondanos

ASP-DAC 2003 3A-2

Towards On-Chip Fault-Tolerant Communication

Carnegie Mellon University, USA
T. Dumitras, S. Kerner, R. Marculescu

ASP-DAC 2003 3C-1

Statistical Delay Computation Considering Spatial Correlations

University of Michigan, USA
A. B. Agarwal, D. Blaauw
Motorola,USA
S. Sundareswaran, V. Zolotov, M. Zhao, K. Gala, R. Panda

ASP-DAC 2003 5D-2s

Design of a Scalable RSA and ECC Crypto-Processor

National Tsing Hua University, Taiwan
M.-C. Sun, C.-P. Su, C.-T. Huang, C.-W. Wu

ASP-DAC 2002 8A-4

Floorplan Evaluation with Timing Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing

C. Albrecht, A. B. Kahng, Ion Mandoiu, A. Zelikovsky ? Univ. of California, San Diego, USA

ASP-DAC 2002 7C-1

Mode Selection and Mode dependency Modeling for Power Aware Embedded Systems

Deixin Li, Pai H. Chou, Nader Bagherzadeh – Univ. of California, Irvine, USA

ASP-DAC 2001 B1-1

Correlation Method of Circuit-Performance and Technology Fluctuations for Improved Design Reliability

Hiroshima Univ., Japan
D. Miyawaki, S. Matsumoto, H. J. Mattausch, S. Ooshiro, M. Suetake, M.Miura-Mattausch
Semiconductor Technology Academic Research Center, Japan
S. Kumashiro, T. Yamaguchi, K. Yamashita,N. Nakayama

ASP-DAC 2001 C6-3

Design Rewiring Based on Diagnosis Techniques

Univ. of Toronto, Canada
A. Veneris
Motorola Inc, USA
M. S. Abadir
Alcatel Corp, Canada
I. Ting

ASP-DAC 2000 D3-1

Delay-Optimal Wiring plan for the Microprocessor of high Performance Computing machines

Jun Kikuchi, Tetsuo Sasaki, Tohru hashimoto and Kazuhisa Miyamoto

ASP-DAC 2000 D6-1

A Cell synthesis Method for Salicide Process

Kazuya Okada, Takayuki Yamanouchi and Takashi Kambe

ASP-DAC 2000 E4-2

Circuit Performance Oriented Device Optimization using BSIM3 Pre-Silicon Model Parameters

Mikako Miyama and Shiro Kamohara

ASP-DAC 1998 2C-3

Concurrent Technology, Device, and Circuit Development for EEPROMs

U. Feldmann, R. Kakoschke, M. Miura-Mattaush, G. Schraud

ASP-DAC 1998 3C-1

On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design

Mohit Sahni, Takashi Nanya

ASP-DAC 1995 6A-2

Maple-opt: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Performance Optimization

Waseda Univ., Japan
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

ASP-DAC 1995 3B-1

Power Analysis of a 32-bit Embedded Microcontroller

Princeton Univ., USA
Vivek Tiwari
Fujitsu Labs. of America, USA
Mike Tien-Chien Lee