| Title | A Wireless Real-Time On-Chip Bus Trace System |
| Author | *Shusuke Kawai, Takayuki Ikari (Keio University, Japan), Yutaka Takikawa (Renesas Design Corp, Japan), Hiroki Ishikuro, Tadahiro Kuroda (Keio University, Japan) |
| Page | pp. 91 - 92 |
| Keyword | Inductive coupring, Wireless interface |
| Abstract | A 480Mb/s wireless real-time bus trace system with a pulse-based inductive coupling channel array was developed using a 0.25m CMOS digital process. The size and pitch of the inductor array are determined by numerical calculation to optimize the tradeoff between the channel coupling, crosstalk, and alignment tolerance. A low-power quasi-synchronous system is proposed to obtain an enough timing margin for RX pulse detection under the presence of the clock skew |
| Slides |
| Title | CKVdd: A Self-Stabilization Ramp-Vdd Technique for Dynamic Power Reduction |
| Author | Chin-Hsien Wang, *Ching-Hwa Cheng (Feng Chia University, Taiwan), Jiun-In Guo (National Chung Cheng University, Taiwan) |
| Page | pp. 93 - 94 |
| Keyword | Low power |
| Abstract | We propose a self-stabilized ramp voltage technique, CKVdd, to reduce power dissipation in conventional CMOS circuit. Normal CMOS circuits show a power increase proportional to clock frequency. CKVdd results in a lower-than-usual power increase. This technique is easily implemented in CMOS circuits. CKVdd technique possesses several characteristics that differ from of the current circuits using Vdd power source. First, CKVdd circuits have less average current and peak current consumption, such that it can be a low power design technique applied to generic digital circuits. Second, CKVdd technique combines the power source and clock signal, and can easily implement the power management mechanism. Compared to constant Vdd for multimedia decoders, the proposed technique has 45% of the usual power dissipation and 88% of the usual peak current reduction at the cost of small delay penalty. |
| Slides |
| Title | A 300 nW, 7 ppm/℃ CMOS Voltage Reference Circuit based on Subthreshold MOSFETs |
| Author | *Ken Ueno (Hokkaido University, Japan), Tetsuya Hirose (Kobe University, Japan), Tetsuya Asai, Yoshihito Amemiya (Hokkaido University, Japan) |
| Page | pp. 95 - 96 |
| Keyword | Voltage reference, subthreshold, Ultra-low power, process variation |
| Abstract | An ultra-low power CMOS voltage reference circuit has been fabricated in a 0.35-um standard CMOS process. The circuit generates a reference voltage based on threshold voltage of a MOSFET at absolute zero temperature. Theoretical analyses and experimental results showed that the circuit generates a quite stable reference voltage of 745 mV on average. The temperature coefficient and line sensitivity of the circuit were 7 ppm/degC and 20 ppm/V, respectively. The power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The circuit consists of subthreshold MOSFETs with a low-power dissipation of 0.3 uW or less and a 1.5-V power supply. Because the circuit generates a reference voltage based on threshold voltage of a MOSFET in an LSI chip, it can be used as an on-chip process monitoring circuit and as a part of the on-chip process compensation circuit systems. |
| Slides |
| Title | A 100Mbps, 0.19mW Asynchronous Threshold Detector with DC Power-Free Pulse Discrimination for Impulse UWB Receiver |
| Author | *Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai (The University of Tokyo, Japan) |
| Page | pp. 97 - 98 |
| Keyword | Ultra-wideband (UWB), UWB receiver, Threshold detector, Pulse discriminator |
| Abstract | An asynchronous threshold detector for DC-960MHz band impulse ultra-wideband (UWB) receiver is proposed in this paper. It features a DC power-free pulse discriminator. The proposed architecture in 90nm CMOS achieves the lowest power consumption of 0.19mW and energy consumption of 1.9pJ/bit at 100Mbps in the UWB receiver. |
| Slides |
| Title | An Inductor-less MPPT Design for Light Energy Harvesting Systems |
| Author | Hui Shao, *Chi-Ying Tsui, Wing-Hung Ki (The Hong Kong University of Science and Technology, Hong Kong) |
| Page | pp. 101 - 102 |
| Keyword | solar cell, power management, MPPT, energy harvesting |
| Abstract | An inductor-less maximum power point tracker was designed for light energy harvesting systems. We target at systems under different lighting environments and sometimes the solar cell voltage may be low. A charge pump is used to convert the voltage to a higher value. At the same time, the control circuit tunes the charge pump switching frequency to track the system maximum output power point. The design was fabricated and measured to verify the system operation. |
| Slides |
| Title | A 1 GHz CMOS Comparator with Dynamic Offset Control Technique |
| Author | *Xiaolei Zhu (Keio University, Japan), Sanroku Tsukamoto (Fujitsu Laboratories Limited, Japan), Tadahiro Kuroda (Keio University, Japan) |
| Page | pp. 103 - 104 |
| Keyword | Offset cancel, Comparator, A/D converter |
| Abstract | Abstract− A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 x 65 m2 and consumes 380 W. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip. |
| Slides |
| Title | Circuit Design Using Stripe-Shaped PMELA TFTs on Glass |
| Author | *Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada (University of Tokyo, Japan) |
| Page | pp. 105 - 106 |
| Keyword | TFT, PMELA, Design environment, Glass |
| Abstract | A design environment for stripe-shaped PMELA TFTs on glass has been developed and successfully tested. Cell library including standard cells, logic synthesis database, Place and Route rule, layout parasitic extraction rule and transistor models are developed. Measurement results show that the digital circuits designed in this environment work correctly. They also show that the simulation environment is accurate enough for simulating digital circuits. |
| Slides |
| Title | A Time-to-Digital Converter with Small Circuitry |
| Author | Kazuya Shimizu, *Masato Kaneta, HaiJun Lin, Haruo Kobayashi, Nobukazu Takai (Gunma University, Japan), Masao Hotta (Musashi Institute of Technology, Japan) |
| Page | pp. 109 - 110 |
| Keyword | Time-to-Digital Converter, Time Domain Analog Circuit, nano CMOS, Digital Assist Analog Technology, Time Measurement |
| Abstract | This paper describes a Time-to-Digital-Converter (TDC) architecture with small CMOS circuitry as well as fine time resolution better linearity compared to a conventional vernier delay line TDC. The TDC measures the interval time between two signals and it is used in
an all digital PLL and a time-domain ADC.
In the proposed TDC, the number of the delay buffers is half of the
conventional TDC, which leads to small chip area and low power. Also the nonlinearity due to delay mismatch among buffers is reduced, which we have demonstrated by MATLAB simulation. We have also designed and laid out its circuitry using TSMC 0.18um CMOS process, and the chip measurements shows its principle functions as expected. |
| Slides |
| Title | A VDD Independent Temperature Sensor Circuit with Scaled CMOS Process |
| Author | *Hiroki Oshiyama, Toshihiro Matsuda, Kei-ichi Suzuki, Hideyuki Iwata (Toyama Prefectural University, Japan), Takashi Ohzone (Dawn Enterprise Co. Ltd., Japan) |
| Page | pp. 111 - 112 |
| Keyword | CMOS, temperature sensor, voltage reference |
| Abstract | A supply voltage (VDD) independent temperature sensor circuit by a standard 90 nm CMOS process achieves the predicted errors about -1.0 to +2.0 C (-0.6 to +0 C) for the temperature range of -20 to +100 C (+20 to +80 C) for two-point calibration lines. This temperature sensor has a good tolerance to the change of VDD from 2.5 to 1.5 V, which corresponds to the measurement error of 0.9 C. |
| Slides |
| Title | Ultra Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids |
| Author | *Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li (National Chiao Tung University, Taiwan), Chou-Kun Lin (ITRI, STC, Taiwan), Chih-Wei Liu (National Chiao Tung University, Taiwan) |
| Page | pp. 115 - 116 |
| Keyword | hearing aid, filter bank, low power |
| Abstract | This paper presents an ANSI S1.11-compliant filter bank for digital hearing aids, of which the power consumption is minimized through algorithmic, numerical and architectural optimizations. This filter bank has been implemented and fabricated using the TSMC 0.13m CMOS technology. The transistor-level simulations show that the power dissipation is only 79W for 24KHz & 18-band audio processing. |
| Slides |
| Title | An 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array with a Photodiode Memory Architecture |
| Author | Daisaku Seto, *Minoru Watanabe (Shizuoka University, Japan) |
| Page | pp. 117 - 118 |
| Keyword | ORGAs, FPGAs, optical configuration, multi-context devices |
| Abstract | The worldfs largest 11,424 gate-count dynamic optically
reconfigurable gate array VLSI chip, which is based on
the use of junction capacitance of photodiodes as configuration
memory, has been fabricated. The size and process of the VLSI
chip are, respectively, a 96.04 mm2 and a 0.35 m-3 metal CMOS
process technology. To clarify the availability of the VLSI, this
paper shows an experimental result of |
| Slides |
| Title | A Low-Power FPGA Based on Autonomous Fine-Grain Power-Gating |
| Author | *Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku University, Japan) |
| Page | pp. 119 - 120 |
| Keyword | FPGA, asynchronous architecture, power-gating, LEDR encoding, bit-serial architecture |
| Abstract | This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell efficiently, asynchronous architecture is full exploited. The proposed FPGA is fabricated in a 90nm CMOS process with dual threshold voltages. It is more efficient in power than the synchronous FPGA at less than 30% utilization. |
| Slides |
| Title | A 52-mW 8.29mm2 19-mode LDPC Decoder Chip for Mobile WiMAX Applications |
| Author | *Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu (Andy) Wu (National Taiwan University, Taiwan) |
| Page | pp. 121 - 122 |
| Keyword | LDPC, Mobile WiMAX, Multi-mode |
| Abstract | This paper presents a LDPC decoder chip supporting
all 19 modes in Mobile WiMAX applications. An efficient IC
design strategy is proposed to reduce 31.25% decoding latency,
and enhance hardware utilization ratio from 50% to 75%. In
addition, we propose a new early termination scheme that can
dynamically adjust the iteration number. The multi-mode chip
implemented in 8.29mm2die area can be maximally measured at
83.3MHz with only 52mW power consumption. |
| Slides |
| Title | A Full-Synthesizable High-Precision Built-In Delay Time Measurement Circuit |
| Author | Ming-Chien Tsai, *Ching-Hwa Cheng (Feng Chia University, Taiwan) |
| Page | pp. 123 - 124 |
| Keyword | Built-in Delay Test, delay fault diagnosis, Vernier Delay Line |
| Abstract | Delay testing has become a major issue for manufacturing advanced Systems on a Chip. Automatic Test Equipment and scan techniques are usually applied in delay testing. However, the circuits under test have many circuit paths and dependent input patterns; it is hard to measure delay times accurately, especially when debugging small delay defects. We propose a Built-In Delay Measurement (BIDM) circuit that is modified from Vernier Delay Lines. All digitally designed BIDMs with small area overhead can be easily embedded within testing circuits. BIDMs can be used to record the data propagation delay times within circuit path segments, for delay testing, diagnosis, and calibration requirements internal to the chip. Our BIDM was implemented in a 32bit error correction circuit by a chip using TSMC 0.18u technology. The instruments measured results showing that the BIDM chip correctly reported the CUT segment path delay times. The chip measurement results were a 95.83% match to the postlayout SPICE simulation values. This BIDM makes it possible to debug small delay defects in chips. |
| Slides |
| Title | A Dynamic Quality-Scalable H.264 Video Encoder Chip |
| Author | *Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen (National Chung Cheng University, Taiwan), Ching-Lung Su (National Yunlin University of Science and Technology, Taiwan), Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang (National Chung Cheng University, Taiwan) |
| Page | pp. 125 - 126 |
| Keyword | Quality-Scalable, H.264, Encoder, real-time |
| Abstract | This paper proposes a dynamic quality-scalable H.264 video encoder that comprises 470Kgates and 13.3Kbytes SRAM using 1P8M 0.13um CMOS technology. Exploiting parameterized algorithms for motion estimation and intra prediction, the proposed design can dynamically configure the encoding modes with the design trade-off between power consumption and video quality for various video encoding applications. It achieves real-time H.264 video encoding on CIF, D1, and HD720@30fps with 7mW-25mW, 27mW-162mW, and 122mW-183mW power dissipation in different quality modes. |
| Slides |
| Title | A High Performance LDPC Decoder for IEEE802.11n Standard |
| Author | *Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto (Waseda University, Japan) |
| Page | pp. 127 - 128 |
| Keyword | LDPC, message passing algorithm, partially-parallel LDPC decoder |
| Abstract | In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction. |
| Slides |
| Title | An 8.69 Mvertices/s 278 Mpixels/s Tile-based 3D Graphics SoC HW/SW Development for Consumer Electronics |
| Author | *Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang (Department of Computer Science and Engineering, National Sun Yat-Sen University, Taiwan) |
| Page | pp. 131 - 132 |
| Keyword | 3D Graphics, SoC, Performance Tuning, Consumer Electronics, Tile-based |
| Abstract | This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm2 tiled-based 3D graphics SoC HW/SW supporting OpenGL ES 1.0 running at 139 MHz. The SoC also includes embedded circuitry to monitor run time characteristics, detect bus protocol error/inefficiency, and capture bus traces at various abstraction levels with compression ratio up to 98%. |
| Slides |
| Title | A Multi-Task-Oriented Security Processing Architecture with Powerful Extensibility |
| Author | *Dan Cao, Jun Han, Xiao-yang Zeng, Shi-ting Lu (Fudan University, China) |
| Page | pp. 133 - 134 |
| Keyword | security processing, multi-core, SoC |
| Abstract | A multi-task-oriented security processing architecture is presented in this paper. This architecture contains a host microprocessor and multiple security processors (SP). The SP could integrate dedicated Crypto-Engines, which provides functional extensibility. And the performance scalability and multi-task parallelism could be enhanced by increasing the number of SPs on system bus. Its demonstrated that this architecture greatly improves the system efficiency. A test chip is implemented based on SMIC 0.18 um standard CMOS technology, and its functionality is well verified. |
| Slides |
| Title | A Delay-Optimized Universal FPGA Routing Architecture |
| Author | *Fang Wu, Huowen Zhang, Lei Duan, Jinmei Lai, Yuan Wang, Jiarong Tong (Fudan University, China) |
| Page | pp. 135 - 136 |
| Keyword | Routing, Delay, GRB |
| Abstract | A universal FPGA routing Architecture is presented, which ensures that every module in the FPGA including CLBs and IOBs have a uniform interconnect architecture, and the load of lines is equally distributed. So, this architecture is highly repeatable and the signal delay is predictable and regular. Furthermore, the realization of the Programmable Interconnect Point (PIP) and the BUFFER driver is also optimized to benefit the signal delay up to 5%.The test results of the example chip show the reasonableness of these ideas. |
| Slides |