Technical Program Committee

Technical Program Chair

Shinji Kimura (Waseda Univ.,Japan)

Technical Program Vice Chairs

Hyunchul Shin (Hanyang Univ.,Korea)
Jing-Jia Liou (National Tsing Hua Univ.,Taiwan)

Secretaries

Nozomu Togawa (Waseda Univ.,Japan)
Shigetoshi Nakatake (Univ. of Kitakyushu.,Japan)

Sub committees and sub committee chairs

[1] System-Level Modeling and Simulation/Verification
*Sri Parameswaran (Univ. of New South Wales, Australia)
Ing-Jer Huang (National Sun Yat-Sen Univ. Taiwan)
Chia-Lin Yang (National Taiwan University Taiwan)
Nagisa Ishiura (Kwansei Gakuin Univ. Japan)
Joerg Henkel (Univ. of Karlsruhe., Germany)
 
[2] System-Level Synthesis and Optimization
*Yuichi Nakamura (NEC Corp., Japan)
Li Shang (Univ. of Colorado, USA)
Danella Zhao (Univ. of Louisiana at Lafayette, USA)
Tsuyoshi Isshiki (Tokyo Institute of Tech., Japan)
Lovic Gauthier (Kyusyu Univ., Japan)
Jen-Chieh Yeh (ITRI, Taiwan)
 
[3] System-Level Memory/Communication Design and Networks on Chip
*Hiroyuki Tomiyama (Nagoya Univ., Japan)
Samar Abdi (Univ. of California, Irvine USA)
Preeti Ranjan Panda (Indian Institute of Technology, Delhi, India)
Tulika Mitra (National Univ. of Singapore, Singapore)
Yoshinori Takeuchi (Osaka Univ., Japan)
Sungjoo Yoo (POSTECH, Korea)
Michihiro Koibuchi (NII, Japan)
Cheng-Yeh Wang (MediaTek Inc., Taiwan)
Yunheung Paek (Seoul National University, Korea)
 
[4] Embedded and Real-Time Systems
*Samarjit Chakraborty (Technical Univ. of Munich, Germany)
Naehyuck Chang (Seoul National. Univ., Korea)
Zonghua Gu (HKUST, Hong Kong)
Chi-Sheng Shih (National Taiwan Univ., Taiwan)
Prabhat Mishra (Univ. of Florida, USA)
Eli Bozorgzadeh (Univ. of California, Irvine, USA)
Zili Shao (Polytechnic Univ., Hong Kong, China)
Chun Jason Xue (City Univ. of Hong Kong, Hong Kong)
Tei-Wei Kuo (National Taiwan Univ., Taiwan)
 
[5] High-Level/Behavioral/Logic Synthesis and Optimization
*Deming Chen (Univ. of Illinois at Urbana-Champaign, USA)
Ani Nahapetian (Univ. of California, Los Angeles, USA)
Hiroyuki Higuchi (Fujitsu Microelectronics Limited, Japan)
Ting-Ting Hwang (National Tsing Hua Univ., Taiwan)
Taewhan Kim (Seoul National Univ., Korea)
Yuan Xie (Pennsylvania State Univ., USA)
Shigeru Yamashita (Ritsumeikan Univ., Japan)
 
[6] Validation and Verification for Behavioral/Logic Design
*Shin'ichi Minato (Hokkaido Univ., Japan)
Yirng-An Chen (Marvell Corp., USA)
Kiyoharu Hamaguchi (Osaka Univ., Japan)
Chung-Yang Huang (National Taiwan Univ., Taiwan)
Miroslav Velev (Aries Design Automation, USA)
Farn Wang (National Taiwan Univ., Taiwan)
Yoshinori Watanabe (Cadence, USA)
 
[7] Physical Design
*Yao-Wen Chang (National Taiwan Univ., Taiwan)
Sheqin Dong (Tsinghua Univ., China)
Jeong-Tyng Li (SpringSoft, USA)
Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Sherief Reda (Brown Univ., USA)
Cliff Sze (IBM Research, USA)
Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, USA)
Evangeline F.Y. Young (The Chinese Univ. of Hong Kong, Hong Kong)
 
[8] Timing, Power Thermal Analysis and Optimization
*Youngsoo Shin (KAIST, Korea)
Matthew Guthaus (Univ. of California, Santa Cruz, USA)
Shih-Hsu Huang (Chung Yuan Christian Univ., Taiwan)
Volkan Kursun (Hong Kong Univ. of Science and Technology, Hong Kong)
Kimiyoshi Usami (Shibaura Institute of Technology, Japan)
Hongliang Chang (Cadence USA)
Massimo Poncino (Politecnico di Torino, Italy)
 
[9] Signal/Power Integrity, Interconnect/Device/Circuit Modeling and Simulation
*Hideki Asai (Shizuoka Univ., Japan)
Kimihiro Ogawa (STARC(Sony) Japan)
Yu-Min Roger Lee (National Chiao Tung Univ. Taiwan)
En-Xiao Liu (Institute of High Performance Computing (IHPC), Singapore)
Zuochang Ye (Tsinghua Univ., China)
Sungroh Yoon (Korea Univ., Korea)
Kyu-won Ken Choi (Illinois Institute of Technology, USA)
 
[10] Design for Manufacturability/Yield and Statistical Design
*Toshiyuki Shibuya (Fujitsu Labs. America, USA)
David Pan (The Univ. of Texas at Austin USA)
Keh-Jeng Chang (National Tsing Hua Univ., Taiwan)
Puneet Gupta (Univ. of California, Los Angeles, USA)
Fedor G. Pikus (Mentor Graphics Corporation, USA)
Zeng Shi (Zhejiang University, China)
 
[11] Test and Design for Testability
*Seiji Kajihara (Kyusyu Institute of Technology, Japan)
Shi-Yu Huang (National Tsing Hua Univ. Taiwan)
Wu-Tung Cheng (Menter Graphics, USA)
Ming-Der Shieh (National Cheng Kung Univ., Taiwan)
Tomokazu Yoneda (NAIST, Japan)
 
[12] Analog, RF and Mixed Signal Design and CAD
*Jaijeet Roychowdhury (Univ. of California, Berkeley, USA)
Alper Demir (Koc Univ., Turkey)
Chin-Fong Chiu (National Chip Implementation Center, Taiwan)
Eric Keiter (Sandia National Labs, Albuquerque, NM, USA)
Woogeun Rhee (Tsinghua Univ., China)
 
[13] Emerging Technologies and Applications
*Chin-Long Wey (National Central Univ., Taiwan)
Arfan Ghani (Univ. of Ulster, N. Ireland UK)
In-Cheol Park (KAIST, Korea))
Mehdi Baradaran Tahoori (Northeastern University, USA)
Chun-Ming Huang (National Chip Implementation Center, Taiwan)
Xiaoyang Zeng (Fudan Univ., China)

Confidentiality