Designers' Forum

Designers' Forum is conceived as a unique program that shares the design experience and solutions of real product developments among hardware/software designers and EDA academia/developers. This year it consists of four special sessions on the topics of SoC development, 3D IC integration, ESL design methodology and embedded software development.

  • Date: January 20-21, 2010
  • Place: Room 101D, Taipei International Convention Center, Taipei,Taiwan
  • Designers' Forum Chair: Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
  • Designers' Forum Vice Chair: Rainer Doemer (Univ. of California, Irvine, USA)
  • Designers' Forum Vice Chair: Alan P. Su (Global Unichip Corp., Taiwan)
  • Designers' Forum Vice Chair: Kunio Uchiyama (Hitachi, Japan)
  • Designers' Forum Vice Chair: Cheng-Wen Wu (National Tsing Hua Univ/ITRI., Taiwan)

 

Date/Time

Title

January 20 / 13:30 - 15:10

Oral Session:
State-of-the-art SoCs

January 20 / 15:30 – 17:10

Tutorial and Panel Discussion:
Is 3D Integration an Opportunity or Just a Hype?

January 21 / 13:30 - 15:10

Oral Session:
ESL, The Road to Glory, Or Is It Not? Real Stories about Using ESL Design Methodology in Product Development

January 21 / 15:30 – 17:10

Oral Session:
Embedded Software Development for Multi-Processor Systems-on-Chip

Designs will be presented focusing mainly on the design styles, problems and ways to tackle these. Panel discussions will also be held concerning the latest design problems. The following gives detailed information of each session:

Session 5D: Wednesday, January 20, 13:30 - 15:10, Room 101D

Oral Session: State-of-the-art SoCs

For digital systems in today’s digital-convergence era, various functions such as communication, security, audio, video, and recognition must be implemented by an SoC. Functional diversification will keep increasing, and demands for the improvement of the SoC's functionality and performance will thus continue. The latest SoCs must meet these requirements while considering cost, power consumption, reliability, and so on. Facing these challenges, new hardware/software technologies and design methodologies are indispensable. In light of our pursuit of advanced technologies for the SoCs, this session is devoted to an exploration of the latest advances in not only hardware/software implementations but also design tools and methods for the developments. Four representatives are invited from both industry and academia, and the state-of-the-art technologies are presented and discussed in the session.

Organizers:
Kunio Uchiyama, Hitachi, Japan

Ing-Jer Huang, National Sun Yat-Sen University, Taiwan

Invited Presentations:

  • 5D-1 : “Overview of ITRI's Parallel Architecture Core (PAC) DSP Project: from VLIW DSP Processor to Android-ready Multicore Computing Platform”
    - An-Yeu (Andy) Wu (STC/ITRI, Taiwan)
     
  • 5D-2 : “Design and Verification Methods of Toshiba's Wireless LAN Baseband SoC (tentative)”
    - Masanori Kuwahara (Toshiba, Japan)
     
  • 5D-3 : “Programmable Platform for Multimedia SoC”
    - Bor-Sung Liang (Sunplus Core Technology, Taiwan)
     
  • 5D-4 : “SoC for Car Navigation Systems with a 53.3 GOPS Image Recognition Engine”
    - Hiroyuki Hamasaki (Renesas Technology, Japan)

 

Session 6D: Wednesday, January 20, 15:30-17:10, Room 101D

  • 6D-1 ：(Tutorial) Is 3D Integration an Opportunity or Just a Hype?

Organizers:
Cheng-Wen Wu, National Tsing-Hua University/ITRI, TW

Jin-Fu Li, National Central University/ITRI, TW

Embedded Tutorial Speaker: JF Li, NCU/ITRI, TW

Three-dimensional (3D) integration using through-silicon via (TSV) provides numerous opportunities to designers looking for more cost-effective system chip solutions. In addition to stacking homogeneous memory dies, 3D integration technology supports heterogeneous integration of memories, logic, sensors, etc. It eases the interconnect performance limitation, provides higher functionality, results in small form factor, etc. On the other hand, there are challenges that should be overcome before volume production of TSV-based 3D ICs becomes possible, e.g., technological challenges, yield and test challenges, thermal and power challenges, infrastructure challenges, etc.

Foundries like IBM and Tezzaron have announced that they are ready for volume shipments of some special chips with 3D technology. Does this mean that 3D integration has a bright future? Or will we eventually see that 3D integration works only for some specific applications?

This session first gives an embedded tutorial which introduces basics of 3D ICs. Then a panel of experts in this area will give position statements and elaborate their perspectives of opportunities and challenges on 3D ICs. Finally, the panel will be open for discussion between the audience and the panelists.
 

  • 6D-2 ：(Panel Discussion)Is 3D Integration an Opportunity or Just a Hype?

Moderator:
Cheng-Wen Wu, NTHU/ITRI

Panelists:
Albert Li, GUC (TW)

Erik Jan rinissen, IMEC (BE)

Ding-Ming Kwai, ITRI (TW)

Kyu-Myung Choi, Samsung (KR)

Makoto Takahashi, Toshiba (JP)

Three-dimensional (3D) integration using through-silicon via (TSV) provides numerous opportunities to designers looking for more cost-effective system chip solutions. In addition to stacking homogeneous memory dies, 3D integration technology supports heterogeneous integration of memories, logic, sensors, etc. It eases the interconnect performance limitation, provides higher functionality, results in small form factor, etc. On the other hand, there are challenges that should be overcome before volume production of TSV-based 3D ICs becomes possible, e.g., technological challenges, yield and test challenges, thermal and power challenges, infrastructure challenges, etc.

Foundries like IBM and Tezzaron have announced that they are ready for volume shipments of some special chips with 3D technology. Does this mean that 3D integration has a bright future? Or will we eventually see that 3D integration works only for some specific applications?

This session first gives an embedded tutorial which introduces basics of 3D ICs. Then a panel of experts in this area will give position statements and elaborate their perspectives of opportunities and challenges on 3D ICs. Finally, the panel will be open for discussion between the audience and the panelists.

 

Session 9D: Thursday, January 21, 13:30 - 15:10, Room 101D

Oral Session: ESL, The Road to Glory, Or Is It Not? Real Stories about Using ESL Design Methodology in Product Development

Electronic System Level design methodology (ESL) has been widely used in leading design houses for SoC designs. However still many designers not adopting the technology. In this session we invite ESL users to share ESL experiences, the road to glory, or not, to help designers make wise decisions in moving into ESL. Designers talk about their experience in using ESL to design real products. Benefit of using ESL, suggestions to adopt ESL design flow and tool package needed to use ESL are discussed. The first talk gives an insight into SW and HW co-design for multi-core SoC based embedded systems, one of the key focuses in ESL. The second talk discusses how ESL not only reduces the development time but also facilitates the communication between algorithm designers and hardware developers. The third talk shows a power estimation framework which uses the proposed power model interface to integrate the various power models in system level for a dual-core SoC. The fourth talk describes how ESL/FPGA co-emulation verification helps the design of a RFID tag.

Organizers:
Alan P. Su, Global Unichip Corp., Taiwan
Ing-Jer Huang, National Sun Yat-sen University, Taiwan

Oral Presentations:

  • 9D-1 : Possibility of ESL- A software centric system design for multicore SoC in the upstream phase
    - Koichiro Yamashita, Fujitsu Laboratories Ltd., Japan
     
  • 9D-2 : Design of Complex Image Processing Systems in ESL Benjamin Carrion Schafer, Ashish Trambadia and Kazutoshi Wakabayashi, NEC Corporation, Japan
     
  • 9D-3 : PAC Duo System Power Estimation Framework at ESL
    - Wen-Tsan Hsieh, Jen-Chieh Yeh and Shi-Yu Huang†, SoC Technology Center, ITRI, Taiwan and National Tsing Hua University†, Taiwan
     
  • 9D-4 : A Practice of ESL Verification Methodology from SystemC to FPGA -Using EPC Class-1 Generation-2 RFID Tag Design as An Example
    - William Young, Chua-Huang Huang†, Alan P. Su‡, C. P. Jou and Fu-Lung Hsueh, TSMC, Feng Chia University†, and Global Unichip Corp.‡, Taiwan

Session 10D: Thursday, January 21, 15:30-17:10, Room 101D

Oral Presentation: Embedded Software Development for Multi-Processor Systems-on-Chip

While embedded system complexities continue to grow exponentially, the software content is constantly increasing, yet the productivity of developing such software is lagging behind that of hardware. In fact, software has become the most important part of the system. For most embedded systems today, it is the software that defines the overall speed, efficiency, power consumption, and capabilities of the system. However, the embedded software is typically only addressed as an afterthought and "shoe horned" into the device.

This session deals with the issues to cope with the ever increasing complexity of embedded systems software. It presents different views by both industry and academia representatives on the challenges and potential solutions for embedded software development for multi-processor systems-on-chip (MPSoC). Two talks from the industrial perspective discuss the issues and challenges involved in developing commercial software for real-world embedded systems, followed by two talks from the academic community that outline promising approaches to automate and overcome key issues in software development for the future.

The first presentation discusses the challenges in developing embedded software across multiple platforms and specifically addresses portability issues in supporting multiple OSes for cell-phone applications. The second presentation addresses low-power aspects in hardware-dependent software that can be optimized using advanced compilation techniques. The third presentation highlights the MAPS compiler, an integrated programming environment for multiple simultaneous applications on MPSoC. MAPS supports both sequential and parallel programming models and targets efficient code generation for predefined heterogeneous MPSoC platforms. The fourth presentation presents research results on system-level modeling of embedded software and automatic code generation for an efficient implementation. Issues including device driver generation and efficient multi-tasking are addressed as well.

Organizers:

Rainer Doemer, University of California at Irvine, USA

Andreas Gerstlauer, University of Texas at Austin, USA

Oral Presentations:

  • 10D-1 : “The Shrink Wrapped Myth: Cross Platform Software”
    - Mike Olivarez (Freescale Semiconductor, Inc., USA)
  • 10D-2 : “Using Software to Achieve Low Power Solutions”
    - Albert Shiue (Alvaview Technologies, Taiwan)
  • 10D-3 : “MPSoC Programming using the MAPS Compiler”
    - Rainer Leupers et al. (RWTH Aachen University, Germany)
  • 10D-4 : “System-level Development of Embedded Software”
    - Gunar Schirner et al. (Northeastern University, USA)