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The 16th Asia and South Pacific Design Automation Conference

Session 2B  Memory Architecture and Buffer Optimization
Time: 13:40 - 15:40 Wednesday, January 26, 2011
Location: Room 413
Chairs: Yu Wang (Tsinghua Univ., China), Yinhe Han (Chinese Academy of Sciences, China)

2B-1 (Time: 13:40 - 14:10)
TitleTemplate-based Memory Access Engine for Accelerators in SoCs
Author*Bin Li, Zhen Fang, Ravi Iyer (Intel Corp., U.S.A.)
Pagepp. 147 - 153
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2B-2 (Time: 14:10 - 14:40)
TitleRealization and Performance Comparison of Sequential and Weak Memory Consistency Models in Network-on-Chip based Multi-core Systems
Author*Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch (Royal Inst. of Tech., Sweden)
Pagepp. 154 - 159
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2B-3 (Time: 14:40 - 15:10)
TitleNetwork-on-Chip Router Design with Buffer-Stealing
AuthorWan-Ting Su, *Jih-Sheng Shen, Pao-Ann Hsiung (National Chung Cheng Univ., Taiwan)
Pagepp. 160 - 164
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2B-4 (Time: 15:10 - 15:40)
TitleMinimizing Buffer Requirements for Throughput Constrained Parallel Execution of Synchronous Dataflow Graph
AuthorTae-ho Shin (Seoul National Univ., Republic of Korea), Hyunok Oh (Hanyang Univ., Republic of Korea), *Soonhoi Ha (Seoul National Univ., Republic of Korea)
Pagepp. 165 - 170
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