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The 16th Asia and South Pacific Design Automation Conference

Session 4C  Architecture Design and Reliability
Time: 10:20 - 12:20 Thursday, January 27, 2011
Location: Room 414+415
Chairs: Shigeru Yamashita (Ritsumeikan University, Japan), Rolf Drechsler (University of Bremen, Germany)

4C-1 (Time: 10:20 - 10:50)
TitleArea-Efficient FPGA Logic Elements: Architecture and Synthesis
Author*Jason Anderson (University of Toronto, Canada), Qiang Wang (Xilinx, Inc., U.S.A.)
Pagepp. 369 - 375
KeywordFPGAs, synthesis, architecture, logic density, technology mapping
AbstractWe consider architecture and synthesis techniques for FPGA logic elements (function generators) and show that the LUT-based logic elements in modern commercial FPGAs are over-engineered. Circuits mapped into traditional LUT-based logic elements have speeds that can be achieved by alternative logic elements that consume considerably less silicon area. We introduce the concept of a trimming input to a logic function, which is an input to a K-variable function about which Shannon decomposition produces a cofactor having fewer than K−1 variables. We show that trimming inputs occur frequently in circuits and we propose low-cost asymmetric FPGA logic element architectures that leverage the trimming input concept, as well as some other properties of a circuit’s AND-inverter graph (AIG) functional representation. We describe synthesis techniques for the proposed architectures that combine a standard cut-based FPGA technology mapping algorithm with two straightforward procedures: 1) Shannon decomposition, and 2) finding non-inverting paths in the circuit’s AIG. The proposed architectures exhibit improved logic density versus traditional LUT-based architectures with minimal impact on circuit speed.
Slides

4C-2 (Time: 10:50 - 11:20)
TitleSelectively Patterned Masks: Structured ASIC with Asymptotically ASIC Performance
Author*Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin (Korea Advanced Institute of Science and Technology, Republic of Korea)
Pagepp. 376 - 381
Keywordstructured ASIC, selectively patterned masks
AbstractWe propose a new lithography method called selectively patterned masks (SPM). It exploits special masks called masking masks and double exposure technique to allow more than one types of tiles to be patterned on the same wafer, thereby relaxing the regularity of structured ASIC. We propose a new structured ASIC based on SPM and assess it using 45-nm technology; experimental result showed substantial improvement over conventional structured ASIC, achieving 1.2x delay and 2.0x area over ASIC design.
Slides

4C-3 (Time: 11:20 - 11:50)
TitleA Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization
Author*Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang (Ric) Huang (National Taiwan University, Taiwan)
Pagepp. 382 - 387
KeywordECO, spare cell, technology mapping
AbstractECO re-mapping is a key step in functional ECO tools. It implements a given patch function on a layout database with a limited spare cell resource. Previous ECO re-mapping algorithms are based on existing technology mappers. However, these mappers are not designed to consider the resource limitation and thus the corresponding ECO results are generally not good enough, or even become much worse when the spare cells are sparse. In this paper, we proposed a new solution for ECO re-mapping. It includes a robust resource-constraint-aware technology mapper and a fast incremental router for wire-length optimization. Moreover, we adopt a Pseudo-Boolean solver to search feasible solutions when the spare cells are sparse. Our experimental results show that our ECO engine can outperform the previous tool in both runtime and routing costs. We also demonstrate the robustness of our tool by performing ECOs on various spare cell limitations.
Slides

4C-4 (Time: 11:50 - 12:20)
TitleSETmap: A Soft Error Tolerant Mapping Algorithm for FPGA Designs with Low Power
AuthorChi-Chen Peng, Chen Dong, *Deming Chen (University of Illinois at Urbana-Champaign, U.S.A.)
Pagepp. 388 - 393
KeywordTechnology Mapping, FPGA, SEU, Low Power, Soft Error
AbstractField programmable gate arrays (FPGAs) are widely used in VLSI applications due to their flexibility to implement logical functions, fast total turn-around time and low none-recurring engineering cost. SRAM-based FPGAs are the most popular FPGAs in the market. However, as process technologies advance to nanometer-scale regime, the issue of reliability of devices becomes critical. Soft errors are increasingly becoming a reliability concern because of the shrinking process dimensions. In this paper we study the technology mapping problem for FPGA circuits to reduce the occurrence of soft errors under the chip performance constraint and power reduction. Compared to two power-optimization mapping algorithms, SVmap [17] and Emap [15] respectively, we reduce the soft error rate by 40.6% with a 2.22% power overhead and 48.0% with a 2.18% power overhead using 6-LUTs.