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The 16th Asia and South Pacific Design Automation Conference

Session 6B  Clock Network Design
Time: 16:00 - 18:00 Thursday, January 27, 2011
Location: Room 413
Chairs: Yuchun Ma (Tsinghua University, China), Youngsoo Shin (Korea Advanced Institute of Science and Technology, Republic of Korea)

6B-1 (Time: 16:00 - 16:30)
TitleAn Optimal Algorithm for Allocation, Placement, and Delay Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs
Author*Kyoung-Hwan Lim, Taewhan Kim (Seoul National University, Republic of Korea)
Pagepp. 503 - 508
KeywordClock skew, Timing
AbstractRecently, it is shown that adjustable delay buffer (ADB) whose delay can be tuned dynamically can be used to solve the clock skew problem effectively under multiple power (voltage) modes.We propose a linear time optimal algorithm that simultaneously solves the problems of computing (1) the minimum number of ADBs to be used, (2) the location at which each ADB is to be placed, and (3) the delay value of each ADB to be assigned to each power mode.
Slides

6B-2 (Time: 16:30 - 17:00)
TitleOn Applying Erroneous Clock Gating Conditions to Further Cut Down Power
Author*Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu (The Chinese University of Hong Kong, Hong Kong)
Pagepp. 509 - 514
Keywordclock gating, logic synthesis, low power, error cancellation
AbstractAll of today's known clock gating techniques only disable clocks on valid ("correct") clock gating conditions, like idle states or observability don’t cares (ODC), whose applying will not change the circuit functionality. In this paper, we explore a technique that allows shutting down certain clocks during invalid cycles, which if applied alone will certainly cause erroneous results. However, the erroneous results will be corrected either during the current or later stages by injecting other clock gating conditions to cancel out each other’s error effects before they reach the primary outputs. Under this model, conditions across multiple flip-flop stages can also be analyzed to locate easily correctable erroneous clock gating conditions. Experimental results show that by using this error cancellation technique, a total power (including dynamic and leakage power) cut of up to 23% and in average of around 6% could be stably achieved, no matter with or without applying Power Compiler (which brought a power cut of 4% in average) together. The results indicate that the power saving conditions found by this new technique were nearly orthogonal (independent) to what can be done by the popular commercial power optimization tool. The idea of these new multi-stage logic error cancellation operations can potentially be applied to other sequential logic synthesis problems as well.

6B-3 (Time: 17:00 - 17:30)
TitleLow Power Discrete Voltage Assignment Under Clock Skew Scheduling
AuthorLi Li (Electrical Engineering and Computer Science Department, Northwestern University, U.S.A.), Jian Sun (State Key Lab of ASIC & System, Microelectronics Department, Fudan University, China), Yinghai Lu, *Hai Zhou (Electrical Engineering and Computer Science Department, Northwestern University, U.S.A.), Xuan Zeng (State Key Lab of ASIC & System, Microelectronics Department, Fudan University, China)
Pagepp. 515 - 520
Keywordlow power, voltage assignment, clock skew scheduling
AbstractMultiple Supply Voltage (MSV) assignment has emerged as an appealing technique in low power IC design, due to its flexibility in balancing power and performance. However, clock skew scheduling, which has great impact on criticality of combinational paths in sequential circuit, has not been explored in the merit of MSV assignment. In this paper, we propose a discrete voltage assignment algorithm for sequential circuit under clock scheduling. The sequential MSV assignment problem is first formulated as a convex cost dual network flow problem, which can be optimally solved in polynomial time assuming delay of each gate can be chosen in continuous domain. Then a mincut-based heuristic is designed to convert the unfeasible continuous solution into feasible discrete solution while largely preserving the global optimality. Besides, we revisit the hardness of the general discrete voltage assignment problem and point out some misunderstandings on the approximability of this problem in previous related work. Benchmark test for our algorithm shows 9.2\% reduction in power consumption on average, in compared with combinational MSV assignment. Referring to the continuous solution obtained from network flow as the lower bound, the gap between our solution and the lower bound is only 1.77\%.
Slides

6B-4 (Time: 17:30 - 18:00)
TitleA Practical Method for Multi-domain Clock Skew Optimization
Author*Yanling Zhi (State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, China), Hai Zhou (Department of Electrical Engineering and Computer Science, Northwestern University, U.S.A.), Xuan Zeng (State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, China)
Pagepp. 521 - 526
KeywordClock Skew Optimization, Multi-Domain
AbstractClock skew scheduling is an effective technique in performance optimization of sequential circuits. However, with process variations, it becomes more difficult to reliably implement a wide spectrum of clock delays at the registers. Multidomain clock skew scheduling is a good option to overcome this limitation. In this paper, we propose a practical method to efficiently and optimally solve this problem. A framework based on branch-and-bound is carefully designed to search for the optimal clocking domain assignment, and a greedy clustering algorithm is developed to quickly estimate the upper bound of cycle period for a given branch. Experiment results on ISCAS89 sequential benchmarks show both the optimality and efficiency of our method compared with the previous work.
Slides