| Title | Robust Clock Tree Synthesis with Timing Yield Optimization for 3D-ICs |
| Author | *Jae-Seok Yang, Jiwoo Pak (Univ. of Texas, Austin, U.S.A.), Xin Zhao, Sung Kyu Lim (Georgia Tech, U.S.A.), David Z. Pan (Univ. of Texas, Austin, U.S.A.) |
| Page | pp. 621 - 626 |
| Detailed information (abstract, keywords, etc) | |
| Title | Track Routing Optimizing Timing and Yield |
| Author | Xin Gao, *Luca Macchiarulo (Univ. of Hawaii, Manoa, U.S.A.) |
| Page | pp. 627 - 632 |
| Detailed information (abstract, keywords, etc) | |
| Title | Simultaneous Redundant Via Insertion and Line End Extension for Yield Optimization |
| Author | Shing-Tung Lin (National Tsing Hua Univ., Taiwan), Kuang-Yao Lee (Taiwan Semiconductor Manufacturing Company, Taiwan), *Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Cheng-Kok Koh (Purdue Univ., U.S.A.), Kai-Yuan Chao (Intel Corp., U.S.A.) |
| Page | pp. 633 - 638 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Pruning-based Trace Signal Selection Algorithm |
| Author | *Kang Zhao, Jinian Bian (Tsinghua Univ., China) |
| Page | pp. 639 - 644 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |