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The 16th Asia and South Pacific Design Automation Conference

Session 7C  Physical Design for Yield
Time: 10:20 - 12:20 Friday, January 28, 2011
Location: Room 414+415
Chair: Cliff Sze (IBM, U.S.A.)

7C-1 (Time: 10:20 - 10:50)
TitleRobust Clock Tree Synthesis with Timing Yield Optimization for 3D-ICs
Author*Jae-Seok Yang, Jiwoo Pak (Univ. of Texas, Austin, U.S.A.), Xin Zhao, Sung Kyu Lim (Georgia Tech, U.S.A.), David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Pagepp. 621 - 626
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7C-2 (Time: 10:50 - 11:20)
TitleTrack Routing Optimizing Timing and Yield
AuthorXin Gao, *Luca Macchiarulo (Univ. of Hawaii, Manoa, U.S.A.)
Pagepp. 627 - 632
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7C-3 (Time: 11:20 - 11:50)
TitleSimultaneous Redundant Via Insertion and Line End Extension for Yield Optimization
AuthorShing-Tung Lin (National Tsing Hua Univ., Taiwan), Kuang-Yao Lee (Taiwan Semiconductor Manufacturing Company, Taiwan), *Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Cheng-Kok Koh (Purdue Univ., U.S.A.), Kai-Yuan Chao (Intel Corp., U.S.A.)
Pagepp. 633 - 638
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7C-4 (Time: 11:50 - 12:20)
TitlePruning-based Trace Signal Selection Algorithm
Author*Kang Zhao, Jinian Bian (Tsinghua Univ., China)
Pagepp. 639 - 644
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