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The 16th Asia and South Pacific Design Automation Conference

Session 8C  System-Level Power Optimization
Time: 13:40 - 15:40 Friday, January 28, 2011
Location: Room 414+415
Chairs: Masanori Muroyama (Tohoku University, Japan), Lih-Yih Chiou (National Cheng Kung University, Taiwan)

8C-1 (Time: 13:40 - 14:10)
TitleAVS-Aware Power-Gate Sizing for Maximum Performance and Power Efficiency of Power-Constrained Processors
AuthorAbhishek Sinkar, *Nam Sung Kim (University of Wisconsin-Madison, U.S.A.)
Pagepp. 725 - 730
KeywordMulti-Core Processors, Power-Gating, Adaptive-Voltage-Scaling
AbstractPower-gating devices incur a small amount of voltage drop across them when they are on in active mode, degrading the maximum frequency of processors. Thus, large power-gating devices are often implemented to minimize the drop (thus the frequency degradation), requiring considerable die area. Meanwhile, adaptive voltage scaling has been used to improve yield of power-constrained processors exhibiting a large spread of maximum frequency and total power due to process variations. In this paper, first, we analyze the impact of power-gating device size on both maximum frequency and total power of processors in the presence of process variation. Second, we propose a methodology that optimizes both the size of power-gating devices and the degree of adaptive voltage scaling jointly such that we minimize the device size while maximizing performance and power efficiency of power-constrained processors. Finally, we extend our analysis and optimization for multi-core processors adopting frequency-island clocking scheme. Our experimental results using a 32nm technology model demonstrates that the joint optimization considering both die-to-die and within-die variations reduces the size of power-gating devices by more than 50% with 3% frequency improvement for power-constrained multi-core processors. Further, the optimal size of power-gating devices for multi-core processors using the frequency-island clocking scheme increases gradually while the optimal supply voltage decreases as the number OF cores per die increases.

8C-2 (Time: 14:10 - 14:40)
TitleEnergy/Reliability Trade-offs in Fault-Tolerant Event-Triggered Distributed Embedded Systems
Author*Junhe Gan (Technical University of Denmark, Denmark), Flavius Gruian (Lund University, Sweden), Paul Pop, Jan Madsen (Technical University of Denmark, Denmark)
Pagepp. 731 - 736
KeywordReliability, Mapping, Energy Minimization, System-level Optimization
AbstractThis paper presents an approach to the synthesis of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Our synthesis approach decides the mapping of tasks to processing elements, as well as the voltage and frequency levels for executing each task, such that transient faults are tolerated, the timing constraints of the application are satisfied, and the energy consumed is minimized. Tasks are scheduled using fixed-priority preemptive scheduling, while replication is used for recovering from multiple transient faults. Addressing energy and reliability simultaneously is especially challenging, since lowering the voltage to reduce the energy consumption has been shown to increase the transient fault rate. We presented a Tabu Search-based approach which uses an energy/reliability trade-off model to find reliable and schedulable implementations with limited energy and hardware resources. We evaluated the algorithm proposed using several synthetic and real-life benchmarks.

8C-3 (Time: 14:40 - 15:10)
TitleProfile Assisted Online System-Level Performance and Power Estimation for Dynamic Reconfigurable Embedded Systems
AuthorJingqing Mu, *Roman Lysecky (University of Arizona, U.S.A.)
Pagepp. 737 - 742
Keywordperformance and power estimation, online estimation, dynamic reconfigurable systems
AbstractSignificant research has demonstrated the performance and power benefits of runtime dynamic reconfiguration of FPGAs and microprocessor/FPGA devices. For dynamically reconfigurable systems, in which the selection of hardware coprocessors to implement within the FPGA is determined at runtime, online estimation methods are needed to evaluate the performance and power consumption impact of the hardware coprocessor selection. In this paper, we present a profile assisted online system-level performance and power estimation framework for estimating the speedup and power consumption of dynamically reconfigurable embedded systems. We evaluate the accuracy and fidelity of our online estimation framework for dynamic hardware kernel selection to maximize performance or minimize system power consumption.

8C-4 (Time: 15:10 - 15:40)
TitleBattery-Aware Task Scheduling in Distributed Mobile Systems with Lifetime Constraint
AuthorJiayin Li, *Meikang Qiu (University of Kentucky, U.S.A.), Jian-wei Niu (Beihang University, China), Tianzhou Chen (Zhejiang University, China)
Pagepp. 743 - 748
KeywordBattery-aware, task scheduling, lifetime constraint
AbstractA distributed mobile system consists of a group of mobile devices with different computing powers. These devices are connected by a wireless network. Parallel processing in the distributed mobile system can provide high computing performance. Due to the fact that most of the mobile devices are battery based, the lifetime of mobile system depends on both the battery behavior and the energy consumption characteristics of tasks. In this paper, we present a systematic system model for task scheduling in mobile system equipped with Dynamic Voltage Scaling (DVS) processors and energy harvesting techniques. We propose the battery-aware algorithms to obtain task schedules giving shorter total execution time while satisfying the battery lifetime constraints. The simulations with randomly generated Directed Acyclic Graphs (DAG) show that our proposed algorithms generate better schedules which can satisfy the battery lifetime constraints.