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The 19th Asia and South Pacific Design Automation Conference

Session 1B  Planning and Placement for Design Closure and Manufacturability
Time: 10:40 - 12:20 Tuesday, January 21, 2014
Location: Room 301
Chairs: Shigetoshi Nakatake (Univ. of Kitakyushu, Japan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan)

1B-1 (Time: 10:40 - 11:05)
TitleAnalytical Placement of Mixed-Size Circuits for Better Detailed-Routability
AuthorShuai Li, *Cheng-Kok Koh (Purdue Univ., U.S.A.)
Pagepp. 41 - 46
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1B-2 (Time: 11:05 - 11:30)
TitleLithographic Defect Aware Placement Using Compact Standard Cells Without Inter-Cell Margin
Author*Seongbo Shim, Yoojong Lee, Youngsoo Shin (KAIST, Republic of Korea)
Pagepp. 47 - 52
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1B-3 (Time: 11:30 - 11:55)
TitleStructural Planning of 3D-IC Interconnects by Block Alignment
Author*Johann Knechtel (Dresden Univ. of Tech., Germany), Evangeline F. Y. Young (Chinese Univ. of Hong Kong, Hong Kong), Jens Lienig (Dresden Univ. of Tech., Germany)
Pagepp. 53 - 60
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1B-4 (Time: 11:55 - 12:20)
TitleComprehensive Die-Level Assessment of Design Rules and Layouts
AuthorRani Ghaida (GLOBALFOUNDRIES, U.S.A.), Yasmine Badr (Univ. of California, Los Angeles, U.S.A.), Mukul Gupta (Qualcomm, U.S.A.), Ning Jin (GLOBALFOUNDRIES, U.S.A.), *Puneet Gupta (Univ. of California, Los Angeles, U.S.A.)
Pagepp. 61 - 66
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