| Title | Physical-Aware Task Migration Algorithm for Dynamic Thermal Management of SMT Multi-Core Processors |
| Author | Bagher Salami (Ferdowsi University of Mashhad, Iran), Mohammadreza Baharani (University of Tehran, Iran), Hamid Noori (Ferdowsi University of Mashhad, Iran), *Farhad Mehdipour (Kyushu University, Japan) |
| Page | pp. 292 - 297 |
| Keyword | dynamic thermal management, multi-core processors, SMT, DVFS, task migration |
| Abstract | This paper presents a task migration algorithm for dynamic thermal management of SMT multi-core processors. The unique features of this algorithm include: 1) considering SMT capability of the processors for task scheduling, 2) using adaptive task migration threshold, and 3) considering cores physical features. This algorithm is evaluated on a commercial SMT quad-core processor. The experimental results indicate that our technique can significantly decrease the average and peak temperature compared to Linux standard scheduler, and two well-known thermal management techniques. |
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| Title | Agile Frequency Scaling for Adaptive Power Allocation in Many-Core Systems Powered by Renewable Energy Sources |
| Author | *Xiaohang Wang, Zhiming Li (Guangzhou Institute of Advanced Technology, CAS, China), Mei Yang, Yingtao Jiang (University of Nevada, Las Vegas, U.S.A.), Masoud Daneshtalab (University of Turku, Finland), Terrence Mak (The Chinese University of Hong Kong, China) |
| Page | pp. 298 - 303 |
| Keyword | power allocation, many-core |
| Abstract | As low-power electronics and miniaturization conspire to populate the world with emerging devices, one appealing approach is to power these multi-core/many-core-based devices with energy harvested from various environments. Of the most important issues concerning these devices is how to effectively allocate power budget among the cores competing for power, which is formulated as one specific type of power-performance optimization problem in this paper. We attempt to solve this problem by proposing an Adaptive Power Allocation Technique (APAT) that explores a dynamic programming network. Our goal here is to maximize the overall system performance, taking into account a unique yet challenging fact that, available power budget might have to undergo a significant change when a renewable energy source is scavenging. APAT has a linear time complexity and low hardware overhead. Experiments have confirmed that APAT can reduce 20- 30% of execution time compared to other state-of-the-art power allocation algorithms. In addition, as APAT is quite insensitive to the changing rate of the power, lending itself well for power management in many-core systems powered by energy-harvesting sources. |
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| Title | Variation Aware Voltage Island Formation for Power Efficient Near-Threshold Manycore Architectures |
| Author | *Ioannis Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano (Politecnico di Milano, Italy) |
| Page | pp. 304 - 310 |
| Keyword | Near Threshold Computing, Voltage Island, Variability Aware Design, Dark Silicon, Power Aware Manycore Design |
| Abstract | The Power Wall problem is gaining a lot of attention as the main stopper to feasible/efficient scaling in the manycore era. In this paper, we introduce a variability aware voltage island formation framework for exploring the potential of NTV power efficiency. By analyzing the voltage island granularities, we show that there is a strong dependence between the efficacy of NTV operation and the parallelism scaling of the application. Operating a 128 core chip at NTV region significant power gains are delivered. |
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| Title | An Evaluation of an Energy Efficient Many-Core SoC with Parallelized Face Detection |
| Author | *Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori (Toshiba Corporation, Japan) |
| Page | pp. 311 - 316 |
| Keyword | many-core, NoC, image recognition, face detection |
| Abstract | We have developed a many-core SoC that includes two many-core clusters with 32 energy efficient processor cores connected by a low latency tree-based NoC. In this paper, we evaluate performance of many-core SoC by face detection as an example of real image recognition applications and discuss two parallelized implementations on the many-core clusters. By keeping balance of workloads on the cores, the performance scales up to 64 cores and the SoC consumes only 2.21W. |
| Slides |
| Title | Energy Aware Real-Time Scheduling Policy with Guaranteed Security Protection |
| Author | *Wei Jiang (School of Computer Science and Engineering, University of Electronic Science and Technology of China, China), Ke Jiang (Department of Computer and Information Science, Linköping University, Sweden), Xia Zhang (School of Information and Software Engineering, University of Electronic Science and Technology of China, China), Yue Ma (Department of Computer Science and Engineering, University of Notre Dame, U.S.A.) |
| Page | pp. 317 - 322 |
| Keyword | Real-time System, Security, Energy, Scheduling |
| Abstract | In this work, we address the emerging scheduling problem existed in the design of secure and energy-efficient real-time embedded systems. The objective is to minimize the energy consumption subject to security and schedulability constraints. Due to the complexity of the problem, we propose a dynamic programming based approximation approach to find the near-optimal solutions with respect to predefined security constraint. The proposed technique has polynomial time complexity which is about half of traditional approximation approaches. The efficiency of our algorithm is validated by extensive experiments. |
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