| Title | No△:Leveraging Delta Compression for End-to-End Memory Access in NoC Based Multicores |
| Author | *Jia Zhan, Matt Poremba (The Pennsylvania State University, U.S.A.), Yi Xu (AMD Research, China), Yuan Xie (Advanced Micro Devices, China/Pennsylvania State University, U.S.A.) |
| Page | pp. 586 - 591 |
| Keyword | Network-on-Chip, Data Compression |
| Abstract | As the number of on-chip processing elements increases, the interconnection backbone bears bursty traffic from memory and cache access. In this paper, we propose a compression technique called No△, which leverages delta compression to compress network traffic. Specifically, it conducts data encoding prior to packet injection and decoding before ejection in the network interface. The key idea of No△ is to store a data packet in the Network-on-Chip as a common base value plus an array of relative differences (△). It can improve the overall network performance and achieve energy savings because of the decreased network load. Moreover, this scheme does not require modifications of the cache storage design and is complementary to any optimization techniques for the on-chip interconnect. Our experiments reveal that the proposed No△ incurs negligible overhead and outperforms state-of-the-art zero-content
compression and frequent-value compression. |
| Slides |
| Title | DPA: A Data Pattern Aware Error Prevention Technique for NAND Flash Lifetime Extension |
| Author | Jie Guo, Zhijie Chen (University of Pittsburgh, U.S.A.), Danghui Wang (Northwestern Polytechnical University, China), Zili Shao (The Hong Kong Polytechnic University, Hong Kong), *Yiran Chen (University of Pittsburgh, U.S.A.) |
| Page | pp. 592 - 597 |
| Keyword | NAND flash, Error pattern, Endurance |
| Abstract | Previous works reveal that the bit error rate of a
NAND flash cell is highly dependent on the stored data patterns.
Based on this observation, we propose a Data Pattern Aware
(DPA) error protection technique to extend the lifespan of NAND
flash based storage systems. DPA manipulates the ratio of 1’s
and 0’s in the stored data to reduce the probability of the
data patterns which are susceptible to noise. By minimizing the
vulnerable data patterns, our scheme can effectively reduce the
bit error rate and therefore improves the system endurance. The
simulation result shows that DPA scheme can increase the flash
system life expectancy by up to 4×, complementing the efforts
of other orthogonal techniques like wear-leveling. |
| Slides |
| Title | Scattered Refresh: An Alternative Refresh Mechanism to Reduce Refresh Cycle Time |
| Author | *T. Venkata Kalyan, Ravi Kasha, Madhu Mutyam (Indian Institute of Technology - Madras, India) |
| Page | pp. 598 - 603 |
| Keyword | DRAM, High-density, Refresh, Row-Mapping |
| Abstract | With realization of high density DRAM devices, the amount of time spent in refreshing a DRAM bank is increasing. This reduces the availability of the bank to the requests from the processing cores, leading to degradation in performance. In this work we target to reduce the refresh cycle time of the DRAM device by scattering the rows in a refresh operation to different subarrays and leveraging the available parallelism in their access. Considering 8Gb devices, we show that Scattered Refresh achieves up to 10.2% of overall system performance improvement. Scattered Refresh being orthogonal to the existing refresh handling techniques, can be employed along with any of them, boosting their effectiveness further. |
| Slides |
| Title | A Read-Write Aware DRAM Scheduling for Power Reduction in Multi-Core Systems |
| Author | *Chih-Yen Lai, Gung-Yu Pan, Hsien-Kai Kuo (Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Taiwan), Jing-Yang Jou (Department of Electrical Engineering and Department of Electronics Engineering, National Central University/Institute of Electronics, National Chiao Tung University, Taiwan) |
| Page | pp. 604 - 609 |
| Keyword | Low power, DRAM, Scheduling, Multi-core |
| Abstract | The demand of high performance and low power has increased the importance of power efficiency in multi-core systems.
In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling have been intensively studied to reduce the power.
However, the benefit of reordering is not fully explored by the previous studies.
To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling.
When compared to the existing work, the proposed techniques reduce 10% more DRAM power with slight performance degradation. |
| Slides |
| Title | A Coherent Hybrid SRAM and STT-RAM L1 Cache Architecture for Shared Memory Multicores |
| Author | *Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong (National University of Singapore, Singapore), Zhenyu Sun, Hai (Helen) Li (University of Pittsburgh, U.S.A.) |
| Page | pp. 610 - 615 |
| Keyword | Cache, STT-RAM, MESI |
| Abstract | STT-RAM is an emerging NVRAM technology that promises high density, low energy and a comparable access speed to conventional SRAM. This paper proposes a hybrid L1 cache architecture that incorporates both SRAM and STT-RAM. By exploiting the MESI coherence protocol to perform dynamic block reallocation between different cache partitions, our hybrid scheme achieves 38% of energy saving with a mere 0.8% decline in IPC while extends the lifespan of STT-RAM partition. |
| Slides |