| Title | Implicit Intermittent Fault Detection in Distributed Systems |
| Author | *Peter Waszecki, Matthias Kauer, Martin Lukasiewycz (TUM CREATE, Singapore), Samarjit Chakraborty (TU Munich, Germany) |
| Page | pp. 646 - 651 |
| Keyword | fault detection, distributed systems, reliability, automotive |
| Abstract | This paper presents a novel approach to detect
resources in distributed systems with an increased occurrence
of intermittent faults that exceed the amount of unavoidable
transient faults caused by environmental phenomena. Intermittent
faults occur due to stressed resources and often are
a precursor of permanent faults. The proposed early fault
detection and diagnosis allows the use of precautionary measures
before the permanent failure of a component in a distributed
system occurs. In this paper, we present four methods that can
implicitly detect intermittent faults by taking the distributed
applications and their dependencies into account. Thus, explicit
tests are not required which would lead to additional costs and
resource load. On the other hand, the implicit approach may
considerably reduce the number of plausibility tests compared to
the conservative solution with one test per resource. We analyzed
and evaluated implementations of the proposed fault detection
principle. The experimental results give evidence of the feasibility
of our approach and show a comparison of the implemented
methods in terms of runtime and detection rate. |
| Slides |
| Title | A Segmentation-Based BISR Scheme |
| Author | Georgios Zervakis, Nikolaos Eftaxiopoulos, Kostas Tsoumanis, Nicholas Axelos, *Kiamal Pekmestzi (National Technical University of Athens, Greece) |
| Page | pp. 652 - 657 |
| Keyword | Built-In Self-Repair, segmentation-based, reparability, memory |
| Abstract | With memory estate increasing in System-On-Chips and highly integrated products, memory defects and wearout effects are the determining factor in the chip’s yield loss and reliability. In this paper, a multiple cache-based Built-In Self-Repair scheme is proposed that is able to repair from the word level down to the bit level. Moreover, it is proved that the level of segmenta-tion does not affect the repair efficiency. An exploration is then conducted to find the optimal scheme in terms of area over-head. |
| Slides |
| Title | Fault-Tolerant TSV by Using Scan-Chain Test TSV |
| Author | *Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang (National Tsing Hua University, Taiwan) |
| Page | pp. 658 - 663 |
| Keyword | 3-D IC, through-silicon-via, redundant TSV, 3D scan-chain, Fault-tolerant |
| Abstract | In order to increase the yield of 3-D IC, fault-tolerance technique to recover failed TSV is essential. In this paper, an architecture of TSV recovery by using scan-chain test TSV is proposed. With the architecture, only a small amount of redundant TSVs is required to be inserted. Extra TSV area that occurs by our method is much less than that of other methods. Moreover, a 3D-IC scan-chain optimization algorithm is proposed taking into consideration the locations of functional TSVs as well as test TSVs, so that the number of total TSVs including test TSV and extra redundant TSV of a 3-D IC design is effectively reduced. |
| Slides |
| Title | Suppressing Test Inflation in Shared-Memory Parallel Automatic Test Pattern Generation |
| Author | Jerry C. Y. Ku, Ryan H.-M. Huang, Louis Y. -Z. Lin, *Charles H.-P. Wen (Dept. of Elec. Comp. Engr., National Chiao Tung University, Taiwan) |
| Page | pp. 664 - 669 |
| Keyword | parallel ATPG, test inflation |
| Abstract | Multi-core machines enable the possibility of parallel
computing in Automatic Test Pattern Generation (ATPG).
With sufficient computing power, previously proposed parallel
ATPG has reached near linear speedup. However, test inflation in
parallel ATPG yet arises as a critical problem and limits its practicality.
Therefore, we developed a parallel ATPG system that incorporates
(1) concurrent interruption (CI), (2) ripple compaction
(RC) and (3) fan-in-cone based fault ordering (FIC) to deal with
such problem. Concurrent interruption aborts test generation on
simultaneously detected faults by fault simulation. Ripple compaction
combines tests for different faults while fan-in-cone based
fault ordering strategically arranges the fault list to reduce the
number of test generations and thus speeds up the ATPG process.
As a result, the proposed parallel ATPG system effectively
reduces 11% pattern count with ~0% test inflation while maintaining
an average of 6.5X speedup with no attenuation in fault
coverage on experimental circuits. |
| Title | A Volume Diagnosis Method for Identifying Systematic Faults in Lower-Yield Wafer Occurring during Mass Production |
| Author | *Tsutomu Ishida, Izumi Nitta (Fujitsu Laboratories LTD., Japan), Koji Banno (Fujitsu Semiconductor LTD., Japan), Yuzi Kanazawa (Fujitsu Laboratories LTD., Japan) |
| Page | pp. 670 - 675 |
| Keyword | Volume diagnosis, Combinatorial optimization |
| Abstract | This work focuses on volume diagnosis for identifying systematic faults in lower-yield wafers, whose yields are lower than baseline level due to systematic faults during mass production. We develop a model-based volume diagnosis method. To diagnose accurately using the fail data with one lower-yield wafer, we apply modeling techniques for handling pseudo-faults and random faults in the fail data. Experimental results show our method’s efficiency; we succeeded in identifying the failure layer for 20/22 data sets with actual lower-yield wafers. |
| Slides |