| Title | Efficient Techniques for the Capacitance Extraction of Chip-Scale VLSI Interconnects Using Floating Random Walk Algorithm |
| Author | *Chao Zhang, Wenjian Yu (Tsinghua University, China) |
| Page | pp. 756 - 761 |
| Keyword | capacitance extraction, floating random walk, Gaussian surface generation, parallel computing |
| Abstract | To enable the capacitance extraction of chip-scale large VLSI layout using the floating random walk (FRW) algorithm, two techniques are proposed. The first one is a virtual Gaussian surface sampling technique. It is used to construct the Gaussian surface for complex nets with vias, and optimizes the sampling and placement of Gaussian surface to reduce the time of random walk. The other one is a parallelized, improved construction approach for Octree based space management structure. It can be over 5000X faster than the existing approach and provides same convenience to the FRW procedure. Numerical experiments on large cases with up to half million conductors validate the proposed techniques, and demonstrate a fast FRW solver for chip-scale extraction task. |
| Slides |
| Title | 3DLAT: TSV-Based 3D ICs Crosstalk Minimization Utilizing Less Adjacent Transition Code |
| Author | *Qiaosha Zou, Dimin Niu, Yan Cao (Pennsylvania State University, U.S.A.), Yuan Xie (Advanced Micro Devices, China/Pennsylvania State University, U.S.A.) |
| Page | pp. 762 - 767 |
| Keyword | 3D IC, capacitive crosstalk, power saving |
| Abstract | 3D integration is one of the promising solutions to overcome the interconnect bottleneck with vertical interconnect through-silicon vias (TSVs). This paper investigates the crosstalk in 3D IC designs, especially the capacitive crosstalk in TSV interconnects. We propose a novel w-LAT coding scheme to reduce the capacitive crosstalk and minimize the power consumption overhead in the TSV array. Combining with the Transition Signaling, The LAT coding scheme restricts the number of transitions in every transmission cycle to minimize the crosstalk and power consumption. Compared to other 3D crosstalk minimization coding schemes, the proposed coding can provide the same delay reduction with affordable overhead. The performance and power analysis show that when w is 4, the proposed LAT coding scheme can achieve 38% interconnect crosstalk delay reduction compared to the data transmission without coding. By reducing the value of w, further reduction can be achieved. |
| Slides |
| Title | Tackling Close-to-Band Passivity Violations in Passive Macro-Modeling |
| Author | *Moning Zhang, Zuochang Ye (Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, China) |
| Page | pp. 768 - 773 |
| Keyword | passivity enforcement, S parameter, state-space model |
| Abstract | Passivity enforcement is important for macromodeling
for passive systems from measured or simulated Sparameter
data. State-space systems generated from vector fitting
usually present strong passivity violation outside the frequency
bandwidth especially in the close-to-band region. Removing such
close-to-band violation is very difficult with exiting passivity
enforcement techniques without severly sacrificing the accuracy
of the model. In this paper we propose a frequency data
extension method which aims to reduce or even eliminated such
close-to-band violations without sacrificing model accuracy. The
generated model can be used in a later stage for further passivity
enforcement. Experiments show that with applying the proposed
method, the accuracy of the generated model can be significantly
improved. |
| Slides |
| Title | HIE-Block Latency Insertion Method for Fast Transient Simulation of Nonuniform Multiconductor Transmission Lines |
| Author | *Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai (Shizuoka University, Japan) |
| Page | pp. 774 - 779 |
| Keyword | block latency insertion method, fast circuit simulation, hybrid implicit-explicit scheme, nonuniform multiconductor transmission lines, numerical stability condition |
| Abstract | This papaer describes a hybrid implicit-explicit block latency insertion method (HIE-block-LIM) for the fast simulation of nonuniform multiconductor transmission lines. In the HIE-block-LIM, an implicit difference method is used with respect to the current variables in one direction, and an explicit method is adopted to update the other variables. The HIE-block-LIM can alleviate a time step size limitation of the existing block-LIM by taking both advantages of the explicit and implicit difference methods. |
| Slides |