TUTORIAL #PD1: Energy-efficient Datacenters

Lead Organizer: Prof. Massoud Pedram (University of Southern California, USA) <pedram@usc.edu>

Speakers: Prof. Massoud Pedram (University of Southern California, USA)

Time: 20 January 2014, 9.00 am - 12.00 pm           Location: Room 303

Tutorial Outline

Pervasive use of cloud computing and the resulting rise in the number of datacenters and hosting centers (which provide platform or software services to clients who do not have the means to set up and operate their own compute facilities) have brought forth many concerns including the electrical energy cost, peak power dissipation, cooling, carbon emission, etc. With power consumption becoming an increasingly important issue for the operation and maintenance of the hosting centers, corporate and business owners are becoming increasingly concerned. Furthermore, provisioning resources in a cost-optimal manner so as to meet different performance criteria such as throughput or response time has become a critical challenge. The goal of this talk is to provide an introduction to resource provisioning and power/thermal management problems in datacenters and to review strategies that maximize the datacenter energy efficiency subject to peak/total power consumption and thermal constraints while at the same time meeting stipulated service level agreements in terms of task throughput and/or response time.

Reference paper: M. Pedram, "Energy-Efficient Datacenters," IEEE Trans. on Computer Aided Design, Vol. 31, No. 10, Oct. 2012, pp. 1465-1484.


TUTORIAL #PD2: Digital Microfluidic Biochips: Towards Hardware/Software Co-Design and Cyber-physical System Integration

Lead Organizer: Prof. Tsung-Yi Ho (National Cheng Kung University, Taiwan) < tyho@csie.ncku.edu.tw >

Speakers: Prof. Tsung-Yi Ho (National Cheng Kung University, Taiwan); and Prof. Krishnendu Chakrabarty (Duke University, USA)

Time: 20 January 2014, 2.00 pm - 5.00 pm                        Location: Room 303

Tutorial Outline

This tutorial will first provide an overview of typical bio-molecular applications (market drivers) such as immunoassays, DNA sequencing, clinical chemistry, etc. Next, microarrays and various microfluidic platforms will be discussed. The next part of the tutorial will focus on electro-wetting-based digital microfluidic biochips. The key idea here is to manipulate liquids as discrete droplets. A number of case studies based on representative assays and laboratory procedures will be interspersed in appropriate places throughout the tutorial. Attendees will learn about CAD, design-for-testability, and reconfiguration aspects of digital microfluidic biochips. Synthesis tools will be described to map assay protocols from the lab bench to a droplet-based microfluidic platform and generate an optimized schedule of bioassay operations, the binding of assay operations to functional units, and the layout and droplet-flow paths for the biochip. The role of the digital microfluidic platform as a “programmable and reconfigurable processor” for biochemical applications will be highlighted. Cyber-physical integration using low-cost sensors and adaptive control, software will be highlighted. Cost-effective testing techniques will be described to detect faults after manufacture and during field operation. On-line and off-line reconfiguration techniques will be presented to easily bypass faults once they are detected. The problem of mapping a small number of chip pins to a large number of array electrodes will also be covered. With the availability of these tools, chip users and chip designers will be able to concentrate on the development and chip-level adaptation of nano-scale bioassays (higher productivity), leaving implementation details to CAD tools.




TUTORIAL #PD3: On Variability and Reliability; Dynamic Margining and Low Power 


Lead Organizer: Prof. Fadi Kurdahi (University of California - Irvine, USA) <kurdahi@uci.edu>

Speakers: Prof. Fadi Kurdahi (University of California - Irvine, USA); Dr. Greg Taylor (Intel Research Lab, USA); Prof. Ahmed Eltawil (University of California - Irvine, USA); and Dr. Amin Khajeh (Intel Research Lab, USA)

Time: 20 January 2014, 9.00 pm - 12.00 pm                       Location: Room 304 Tutorial Outline

The design for manufacturing and yield (DFM&Y) is fast becoming an indispensable consideration in today's SoCs. Most current flows only consider manufacturability and yield at the lowest levels: process, layout and circuit. As such, these metrics are treated as an afterthought. With advanced process nodes, it has become increasingly expensive --and soon prohibitive-- to guarantee bit level error free chips. The challenge now is to design reliable systems using chips that may have some faults, and hence leads to approaches that consider DFM&Y at the system level where more benefit can be reaped, and to consider the problem across the design layers. This tutorial covers cross layer approach to design for DFM&Y spanning from the application all the way to manufacturing, overviews various techniques being explored today, and demonstrates its effectiveness on key applications including wireless communication systems (using 3G and 4G as the transmission physical layer), and multimedia applications (H.264 and H.265). The results confirm that there is a significant opportunity for cross-layer error exploitation, resulting in an expanded design space with interesting design points that would otherwise have not been discovered by SoC designers. We then proceed to describe a scalable, unified statistical model that accurately reflects the impact of random hardware failures (embedded memory as an example) due to power management policies on the overall performance of a communication system. This enables system designers to efficiently and accurately determine the effectiveness of novel power management techniques and algorithms that are designed to manage both hardware failure and communication channel noise. We will also present early work on extending the modeling strategy to logic blocks. To illustrate those concepts, the tutorial will explore application-aware power management technique based on autonomous learning for power management. The tutorial will discuss using techniques such as Q learning to learn the dynamics of the system over time and apply the optimal parameters to save power. This will be presented in the context of a wireless DVB and WiMax system.

TUTORIAL #PD4: Architecture Level Thermal Modeling, Prediction and Management for Multi-core and 3D Microprocessors

Lead Organizer: Prof. Sheldon Tan (University of California - Riverside, USA) <stan@ee.ucr.edu>

Speakers: Prof. Sheldon Tan (University of California - Riverside, USA); and Prof. Hai Wang (University of Electronic Science and Technology, China)

Time: 20 January 2014, 2.00 pm - 5.00 pm                        Location: Room 304

Tutorial Outline

Temperature has become a major concern for high performance microprocessor and package design as more devices are integrated on a chip. This problem becomes more severe as the VLSI technology scales to the nanometer ranges. Excessively high on-chip temperature can cause many severe problems such as reduced reliability of chips and elevated cooling cost of the packaging. As a result, temperature estimation, prediction and runtime thermal management are critical to reduce hot spots, improve reliability for today's high performance multi-core micro-processors.

In the first part of the tutorial, we will describe several new architecture level thermal modeling and analysis techniques.  We will first present moment matching based fast thermal analysis algorithm, called TMM and compare it with HotSpot-based thermal analysis method. We then present a new compact behavioral thermal modeling technique for multi-core microprocessor designs. In the second part of this tutorial, we will present a new method to accurately estimate and predict the full-chip temperature at runtime under more practical conditions where we have inaccurate thermal model, less accurate power estimations and limited number of on-chip physical thermal sensors. The new approach employs a number of new techniques to address this problem by error compensation method, correlation-modeling scheme and time-series power prediction techniques. A number of examples based on Intel quad-core microprocessors will be presented. In the third part of this tutorial, we will present is a new distributed dynamic thermal management scheme for reducing the temperature variations across the chip. Instead of intuitively assigning the heavy tasks to the low temperature cores to balance the thermal profile based on steady state thermal analysis, the new method applies moment matching based frequency-domain thermal analysis techniques for fast thermal estimation and prediction to guide task assignment process. The resulting algorithm can lead to significant reduction of hot spots without full transient thermal simulation, which will benefit the system reliability.

TUTORIAL #SD1: High-Level Specifications to Cope With Design Complexity

Lead Organizer: Prof. Gunar Schirner (Northeastern University, USA) < schirner@ece.neu.edu>

Speakers: Prof. Gunar Schirner (Northeastern University, USA); Prof. Wolfgang Müller (University of Paderborn, Germany); Prof. Eugenio Villar (University of Cantabria, Spain); Prof. Rainer Dömer (University of California at Irvine, USA)

Time: 20 January 2014, 2.00 pm - 5.00 pm                        Location: Room 306

Tutorial Outline

Design abstractions are key to deal with design complexity of high-performance computer system, mobile embedded system, and real-time automobile system. In Electronic System Level (ESL) design we have enjoyed abstractions above the Register Transfer Level (RTL) up to Transaction Level Modeling (TLM). Much research work starts with a behavioral specification of the system functionality captured in a System-Level Description Language (SLDL) and then focuses on identifying heterogeneous allocation, mapping and scheduling. However, less attention has been given on how to obtain such a behavioral specification, which already determines the quality and performance of the final system to a large degree. Crucial aspects already locked down include algorithm quality, parallelization potential (task-, data-, and instruction-level parallelism), demands on local data storage, and amount of traffic. Therefore a sufficiently flexible, parallelism exposing specification is paramount to enable meaningful design space evaluation.
This tutorial discusses the topics of creating and validating a “good” system specification from complementary perspectives. The first talk titled “From Requirements Specification to Executable Testbenches - Methodologies and Standards” deals with how high-level system requirements, captured in a natural language, can be translated into a testbench for validating the specifications correctness. The second presentation “Conceptual Abstraction Levels (CALs): From Concept to Executable Functional Specification” looks into higher abstraction levels that aid the designer in defining a behavioral specification traversing tradeoffs of quality, performance and traffic with a focus on embedded vision systems. The third talk “Modeling and SW synthesis for heterogeneous embedded systems in UML/MARTE” highlights opportunities and methods to describe, simulate and automatically generate the SW stacks on heterogeneous platforms using UML/MARTE. The fourth presentation “Designer-in-the-Loop Recoding to Create Safe Parallel ESL Models” introduces a modeling environment and methodology that aids the system designer in obtaining a model specification with safe parallelism when starting from abundantly available flat C-code.

TUTORIAL #SD2: Many-core and Heterogeneous System-Level Verification Methodology

Lead Organizer: Alex Goryachev (IBM Research - Haifa, Israel) <GORY@il.ibm.com>
Speakers: Mr. Alex Goryachev (IBM Research - Haifa, Israel); and Mr. Ronny Morad (IBM Research - Haifa, Israel)

Time: 20 January 2014, 9.00 am - 12.00 pm                       Location: Room 306

Tutorial Outline

Many companies today employ many-core and heterogeneous architectures for their systems to meet the growing needs of high performance products with low power consumption. These architectures significantly increase the complexity of SoCs, especially at the system-level. Being on the critical path of the product development, system-level verification is the bottleneck for such projects. Traditional verification approaches do not provide an adequate solution to this challenge since they view a system as a combination of individual components, and they concentrate on SW-HW co-verification at the system-level. In this tutorial, we present a proven methodology to deal with such systems. The key points of our methodology are:
–          Treat the system as a whole rather than merely a combination of diverse individual components. By doing so, our method is able to verify complex interdependencies between various system components.
–          Focus on HW-only integration level as opposed to SW and HW. This does not mean SW-HW co-verification is not a required step in system verification: one must verify how the real HW works with the real SW. However, our method does not require the real SW, thus allowing early verification. This also makes our approach more suitable for verifying general-purpose aspects of system architecture that are present in most of the SoCs today.
–          Include technologies and toolset that support the methodology for system- level verification, including test plan definition, intelligent test-case generation, checking, and coverage.
Our methodology has been widely used within IBM across several product lines: Power Systems, System z, as well as gaming consoles and other SoCs. In addition to presenting our methodology, we also address the role of system- level verification in the overall verification cycle, its goals and challenges.

TUTORIAL #SD3: The Formal Specification Level: Bridging the Gap between the Spec and its Implementation

Lead Organizer: Prof. Robert Wille (University of Bremen, Germany) <rwille@informatik.uni-bremen.de>
Speakers: Prof. Robert Wille (University of Bremen, Germany); Dr. Rainer Findenig (Intel Mobile Communication, Austria); and Prof. Rolf Drechsler (DFKI GmbH, Germany)

Time: 20 January 2014, 2.00 pm - 5.00 pm                        Location: Room 307

Tutorial Outline

For the design of modern cyber-physical embedded and automobile system, the starting point of each design process usually is given by means of a textual specification provided in a natural language. But in order to perform even the simplest automatic synthesis techniques, an initial implementation is generated -- usually at the Electronic System Level (ESL) by means of high-level programming languages such as SystemC. This process is expensive, time-consuming, and requires a large number of well-trained design engineers. In fact, this process builds the major bottleneck in today’s design flows. Consequently, designers are constantly striving for higher levels of abstraction to bridge the gap between the initial spec and the resulting implementation. After the gate level, the Register Transfer Level (RTL), and the Electronic System Level (ESL), researchers are increasingly considering the Formal Specification Level (FSL). Here, modeling languages such as the Unified Modeling Language (UML) or the System Modeling Language (SysML) are applied. They allow for a formal specification of the structure and the behavior of a system while, at the same time, abstracting from precise implementation details.
In fact, the FSL is particularly suited to address the bottleneck mentioned above since: 1) initial solutions exist to automatically derive a respective FSL description from a given informal specification using techniques of Natural Language Processing (NLP); 2) crucial design flaws can already be detected at the specification level and, thus, before any line of code is written; and 3) the description means of the FSL provide a proper input for automatic code generation techniques. The tutorial addresses hardware- and software engineers from industry and academia, as well as students of computer science, electrical engineering, or similar areas. The focus is on early phases within the design flow, i.e. the transformation of an initial specification into a first implementation.


TUTORIAL #SD4: High-Level Synthesis for Low-Power Design

Lead Organizer: Prof. Deming Chen (University of Illinois, Urbana-Champaign, USA) <dchen@illinois.edu>
Speakers: Prof. Zhiru Zhang (Cornell University, USA); and Prof. Deming Chen (University of Illinois, Urbana-Champaign, USA)

Time: 20 January 2014, 9.00 am - 12.00 pm                       Location: Room 307

Tutorial Outline

The IC industry has undergone a significant transition from performance-constrained design to power-constrained design. In order to meet stringent power requirement, designers often have to optimize the initial RTL in an ad hoc manner, with consideration of functional, structural, temporal, and spatial information needed for applying various low-power optimization techniques, such as clock and/or power gating, multi- Vdd and multi-clock designs, etc. In this light, high-level synthesis (HLS), which enables automatic generation of optimized hardware from high-level programming languages and facilitates effective exploration of software and hardware architectures, is a promising direction to improve design productivity and at the same time address the increasing difficulty to meet power budgets. In spite of multiple technical challenges of accurately estimating power above the RT level, we believe that promoting power as a first-order design objective is crucial for HLS to attain wider adoption in the design community. Advances in this area have the potential to significantly reduce the turnaround time in achieving the power closure.
In this tutorial, we will first provide an overview of the state-of-the-art HLS technologies, including the general design methodologies, major synthesis steps, and key optimization techniques. In particular, we will dis- cuss the common practices of using commercial/academic HLS tool flows to explore the design space and derive low-power implementations. We will then provide an in-depth coverage of various low-power optimization techniques and synthesis algorithms in HLS, including high-level power estimation techniques, scheduling and binding algorithms for static and dynamic power reductions and behavior-level observability analysis for clock and/or power gating. Tutorial presentations will encompass two segments, with the first segment focusing on the general HLS methodologies and various specific low-power optimization and synthesis techniques, and the second segment on the FCUDA compilation and synthesis flow for energy-efficient computing.


Conference pre-registration through Web is strongly advised. Please visit the online registration page: https://www.elink.com.sg/aspdac2014/registrationNC.asp.


By Nov 15, 2013
(GMT +8)

From Nov 16, 2013
To Jan 19, 2014

On site


* Member

280 SGD

350 SGD

350 SGD


330 SGD

400 SGD

400 SGD

Full-time Student

180 SGD

250 SGD

250 SGD

**Student Group

150 SGD

200 SGD


     * Member of IEEE, ACM SIGDA
     ** “Student Group” discount is applied to a group of four or more students from the same affiliation (faculty or graduate school). A list of the group members must be submitted. Please check the details in the following registration form
     * Member of SSIA get 10% discount.

The tutorial fee includes:

  • Admission to tutorials
  • Access to electronic files of tutorial presentations
  • One refreshment per break

A delegate is eligible for student rate if he/she is a full-time undergraduate or postgraduate student. Students must email a scanned copy of their 'student identification card' for verification and are also required to bring along their 'student identification card' to the conference. Registration under the Student rate will NOT entitle one to attend the Conference Banquet and will NOT entitle one to register any paper. A FULL registration is required for registering a paper.
All registration fees must be paid in Singapore dollar by bank remittance or credit card. Please note that personal checks and bank drafts will not be accepted.
Bank Remittance
Please remit the appropriate amount to the following bank account.
Bank Name: OCBC Bank\(Oversea-Chinese Banking Corporation Bank)
Account Name: IEEE ASP-DAC 2014
Account No.: 514-771914-001
Credit Card
The following credit cards will be accepted: VISA, MasterCard
Cancellation and Refund Policy
When written notification of cancellation is received by the conference secretariat by December 19 2013, 20% of paid costs will be deducted from the fees paid to cover administrative costs. No refunds will be made for cancellation requests received after this date. Speakers are not allowed to cancel registrations.
On-Site Registration (Suntec, Singapore)


January 20:

8:00 – 18:00


January 21

7:00 – 17:00


January 22

7:00 – 17:00


January 23

7:00 – 17:00

ASP-DAC 2014 Tutorial Chair:
Asst. Prof. Yu, Hao Nanyang Technological University, Singapore
Email: haoyu@ntu.edu.sg
ASP-DAC 2014 Secretariat:  A’Tenga C. E.
2 Kallang Pudding Road,
#09-04 Mactech Industrial Building,
Singapore 349307
Email: aspdac2014-sec@mls.aspdac.com
Phone +65-6746-4301 FAX +65-6744-9342




Last Updated on: Oct 23, 2013