Tutorial
Time, Schedule and Fee
| Room : TF 4303 | Room : TF 4203 | |
| 9:00 - 12:00 | Tutorial-1 Machine Learning and Neuromorphic Computing Acceleration |
Tutorial-2 Directed Self-Assembly Lithography (DSAL): Mask Synthesis and Circuit Design |
| 14:00 - 17:00 | Tutorial-3 Uncertainty Quantification for Electronic Systems: State of the Art and Recent Progress |
Tutorial-4 Energy-efficient Data Analytics: Thousand-core Accelerator In-Memory with Reconfigurable I/Os |
Tutorial-1: Machine Learning and Neuromorphic Computing Acceleration
- Time:
- 9:00 - 12:00
- Organizer:
- Prof. Yiran Chen (University of Pittsburgh)
- Speaker:
- Prof. Yu Wang (Tsinghua University)
- Prof. Yiran Chen (University of Pittsburgh)
Biographies:
Yu Wang received his B.S. degree in 2002 and Ph.D. degree (with honor) in 2007 from Tsinghua University, Beijing, China. He is currently an Associate Professor with the Department of Electronic Engineering, Tsinghua University. His research interests include parallel circuit analysis, application specific hardware computing (especially on the Brain Inspired Computing), and power/reliability aware system design methodology. Dr. Wang has authored and coauthored over 130 papers in refereed journals and conferences. He is the recipient of IBM X10 Faculty Award in 2010, Best Paper Award in ISVLSI 2012, Best Poster Award in HEART 2012, and 6 Best Paper Nomination in ASPDAC/CODES/ISLPED. He serves as the Associate Editor for IEEE Trans on CAD, Journal of Circuits, Systems, and Computers. He is the TPC Co-Chair of ICFPT 2011, Finance Chair of ISLPED 2012-2015, and serves as TPC member in many important conferences (DAC, FPGA, DATE, ICCAD, ISLPED, etc.).
Yiran Chen received B.S and M.S. (both with honor) from Tsinghua University and Ph.D. from Purdue University in 2005. After five years in industry, he joined University of Pittsburgh in 2010 as Assistant Professor and then promoted to Associate Professor in 2014. He is now leading Evolutionary Intelligence Lab (www.ei-lab.org) at Electrical and Computer Engineering Department, focusing on the research of nonvolatile memory and storage systems, neuromorphic computing, and mobile systems. Dr. Chen has published one book, a handful of book chapters, and more than 200 journal and conference papers. He has been granted with 90 US and international patents with other 13 pending applications. He is the associate editor of IEEE TCAD, ACM JETC, ACM SIGDA E-news and served on the technical and organization committees of around 40 international conferences. He received three best paper awards from ISQED’08, ISLPED’10 and GLSVLS’13 and other eight nominations from DAC, DATE, ASPDAC, etc. He also received NSF CAREER award in 2013, ACM SIGDA outstanding new faculty award in 2014, and was the invitee of 2013 U.S. Frontiers of Engineering Symposium of National Academy of Engineering (NAE).
Tutorial Outline:
Machine learning (ML) is the enabler of many modern applications like big data analytics, speech and video recognition, natural language processing, robotics etc. The algorithms of ML, especially the recently emerged deep learning ones, often consume a large volume of computation resources and memory. Considering the rapid upscaling pace of the problem size that ML applications face, e.g., increasing one order-of-magnitude per year, the cost of the computer systems that run the ML applications will quickly become unaffordable. Designing a special circuit or hardware system that can accelerate ML applications leads to a promising alternative way to continue scaling up the capacity of the computing platform for ML. The great potential demonstrated by such special circuit and hardware system has gained tremendous attentions from both company and academia, and inspires the corresponding fast-growth industry sector.
In this tutorial, two speakers will cover the a few important topics in machine learning acceleration. At first, Prof. Yu Wang from Tsinghua University will first introduce the basics of the most widely utilized convolutional neural networks (CNN), and then provide an overview of state-of-the-art designs for embedded CNN. Furthermore, their solutions with FPGA and embedded GPU (winner of the LPIRC 2015) will be presented as a case study. After that, Prof. Yiran Chen from University of Pittsburgh will present a systematic approach to design reconfigurable on-chip machine learning acceleration hardware, including the realization on both FPGA platform or as the accelerator augmented to conventional pipeline. The topology and computation flow of the designed circuit can be easily reconfigured to adapt to the requirements of different machine learning applications on resources and their management, achieving 2~3 orders of magnitude performance speedup.
Tutorial-2: Directed Self-Assembly Lithography (DSAL): Mask Synthesis and Circuit Design
- Time:
- 9:00 - 12:00
- Organizer:
- Prof. Youngsoo Shin (KAIST)
- Speaker:
- Prof. Youngsoo Shin (KAIST)
- Mr. Seongbo Shim (Samsung)
Biographies:
Youngsoo Shin received the B.S., M.S., and Ph.D. degrees in electronics engineering from Seoul National University, Korea. From 2000 to 2001, he was a Research Associate with the University of Tokyo, Japan, and from 2001 to 2004 he was a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY. He joined the Department of Electrical Engineering, KAIST, Korea, in 2004, where he is currently a Professor. His current research interests include CAD with emphasis on low-power design and design tools, high-level synthesis, sequential synthesis, and programmable logic. Dr. Shin has received the Best Paper Award at ISQED in 2005. He has been a member of the technical program committees and organizing committees of many conferences including DAC, ICCAD, ISLPED, ASP-DAC, ICCD, and VLSI-SoC. He is an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and the ACM Transactions on Design Automation of Electronic Systems.
Seongbo Shim received the B.S. and M.S. degrees in physics from Seoul National University, Seoul, Korea, in 2004 and 2006, respectively. From 2006, he has been with the Semiconductor R\&D Center, Samsung Electronics, where he was a senior engineer of the computational lithography, OPC, and DFM for the advanced technologies. He has published more than 30 papers on semiconductor manufacturing (lithography and OPC) and DFM. He is the holder of 12 patents on OPC and lithography. His research interests include mask synthesis (OPC) algorithm, DFM, VLSI CAD for design-manufacturing interface, and design technology co-optimization (DTCO) for emerging technologies.
Tutorial Outline:
With continuous down scaling of semiconductor technology, optical lithography has already become the bottleneck for integrated circuit (IC) fabrication. Directed self-assembly lithography (DSAL) is considered as a most promising patterning solution for contact holes and vias in technology node of 7nm and below.
DSAL consists of two steps: optical lithography to form guide patterns (GPs) on a wafer, and DSA to form contacts (or vias) within each GP. A GP, which is a key component of DSAL, poses a few challenges. In mask synthesis, a set of GPs for a given contact layout can only be extracted through lengthy simulations; once GPs are obtained, they should be verified to see whether target contacts are formed, which is also a difficult problem. Contact topologies are limited due to the limitation of GP, which calls for careful consideration in design stages, e.g. during custom layout, placement, and routing.
The goal of this tutorial is to present the basics of DSAL technology and a few state-of-the-art in mask synthesis and design optimization, and to address a number of open research questions and topics. The tutorial will consists of:
- Overview of DSAL technology: Patterning mechanism and flow of DSAL is briefly introduced and compared with those of standard optical lithography. Recent development status and issues will also be covered.
- DSAL Mask Synthesis: Conventional mask synthesis and verification (for optical lithography) are obsolete in DSAL. New problems in mask synthesis and verification will be introduced and addressed: (1) fast yet accurate verification of GP through machine learning, (2) inverse DSA, which tries to synthesize ideal GPs for a given contact layout, and (3) DSAL aware inverse lithography, which tries to find ideal mask for the ideal GP.
- DSAL-Aware Circuit Design: A few circuit design challenges as DSAL is employed are introduced and discussed: (1) strategy of developing design rule, (2) optimization of standard cell layout for DSAL manufacturability, and (3) new placement and routing methodologies for DSAL friendly layout.
Tutorial-3: Uncertainty Quantification for Electronic Systems: State of the Art and Recent Progress
- Time:
- 14:00 - 17:00
- Organizer:
- Prof. Luca Daniel (MIT)
- Speaker:
- Prof. Luca Daniel (MIT)
- Dr. Zheng Zhang (MIT, and Argonne National Labs)
Biographies:
Luca Daniel received the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 2003. He is currently a Full Professor in the Electrical Engineering and Computer Science Department of the Massachusetts Institute of Technology (MIT). Industry experiences include HP Research Labs, Palo Alto (1998) and Cadence Berkeley Labs (2001). His current research interests include integral equation solvers, uncertainty quantification and parameterized model order reduction, applied to RF circuits, silicon photonics, MEMs, Magnetic Resonance Imaging scanners, and the human cardiovascular system. Prof. Daniel was the recipient of the 1999 IEEE Trans. on Power Electronics best paper award; the 2003 best PhD thesis awards from the Electrical Engineering and the Applied Math departments at UC Berkeley; the 2003 ACM Outstanding Ph.D. Dissertation Award in Electronic Design Automation; the 2009 IBM Corporation Faculty Award; the 2010 IEEE Early Career Award in Electronic Design Automation; the 2014 IEEE Trans. On Computer Aided Design best paper award; and seven best paper awards in conferences.
Zheng Zhang received his Ph.D (2015) in Electrical Engineering and Computer Science from MIT, and his M.Phil (2010) from the University of Hong Kong. He is currently a postdoc associate with the Math and Computer Science Division, at the Argonne National Labs. His industrial experience includes Coventor (2011) and Maxim-IC (2012); and his academic visiting experience includes UC San Diego (2009), Brown University (2013) and Politecnico di Milano (2014). His research interests include uncertainty quantification and its interface with tensors, model-order reduction, machine learning and high-dimensional statistics, with applications in nano-scale devices and systems, power systems and MRI. Dr. Zhang received the 2014 Best Paper Award from IEEE Trans. CAD of Integrated Circuits and Systems, the 2014 Chinese Government Award for Outstanding Students Abroad, the 2011 Li Ka-Shing Prize (best thesis award) from the University of Hong Kong, and several best paper nominations at top-tier international conferences.
Tutorial Outline:
The increasing process variations (e.g., material-property variations and geometric imperfection) in nano fabrications have caused lots of performance degradations and functional failures in nano-scale electronic, circuit and system design. In order to support variation-aware and robust chip design, it is highly desirable to develop efficient stochastic modeling and simulation algorithms to characterize such uncertainties. This session first reviews popular uncertainty quantification techniques (e.g., classical sampling-based and intrusive methods, sparse approximation techniques such as compressed sensing) for stochastic electromagnetic field solvers and circuit/MEMS simulation. Then, some advanced computational techniques (such as stochastic model-order reduction, dominant singular-vector methods and tensor-based algorithms) will be introduced to solve the challenging high-dimensional problems in VLSI parasitic extraction, analog/RF circuit and MEMS simulation.
Tutorial-4: Energy-efficient Data Analytics: Thousand-core Accelerator In-Memory with Reconfigurable I/Os
- Time:
- 14:00 - 17:00
- Organizer:
- Prof. Hao YU (Nanyang Technological University)
- Speaker:
- Prof. Hao YU (Nanyang Technological University)
Biographies:
Hao Yu obtained Ph. D degree from electrical engineering department at UCLA in 2007. Since 2010, he has been a faculty at school of electrical and electronic engineering and area directors at VIRTUS (IC design) and Valens (biomedical) centre of excellence, Nanyang Technological University (NTU), Singapore. His primary research interest is in CMOS emerging technology for energy-efficient links and sensors with more than 4M-USD research funding from agency and industry (Intel, Oracle, Huawei, TSMC). He has ~160 peer-reviewed IEEE/ACM/Nature publications, 4 books, 1 best paper award of ACM Transaction, 1 keynote talk, 3 best paper award nominations, 3 student paper competition (advisor) finalists, 1 inventor award from semiconductor research cooperation (SRC), and 10 pending patents. He is associate editor and technical program committee member of many IEEE/ACM international journals and conferences. He is a senior member of IEEE and member of ACM.
Tutorial Outline:
Big-data analytics has scaled up to Exa-scale that is already beyond the scalability of the present technology and architecture. It has thereby raised many new research opportunities to deploy emerging technology and architecture towards building a data server on chip with integrated 1000-acclerator-core and main memory. One fundamental challenge is how to overcome dark silicon dilemma with improved I/O utilization for both power management and data communication. Firstly, we discuss a 2.5D through-silicon-interposer reconfigurable I/O (connection and voltage swing) architecture developed for both scalable power management and data communication in data-server with results reported in DAC’13, ICCAD’14, and CICC’15, where on-chip data analytics is deployed to learn data pattern such that I/Os can be configured for energy-efficient data migration at 1000-core scale. Secondly, we discuss a non-volatile in-memory accelerator (machine-learning) architecture without I/Os. According energy-efficient compressive machine-learning accelerators are developed in both CMOS and memristor with results reported in DATE’15, ISLPED’15 and VLSI-SYMP’15.